`2823a78`

Coerce mixed-width select operands

Authored by

espadonne 3 weeks ago

SHA: 2823a78ac21e0508f5435a2afd4ace6a0461f669
Parents: dad5b04
Tree: 60272a7

2 changed files

Status	File	+	-
M	`src/codegen/isel.rs`	82	2
M	`tests/i128_stack_args.rs`	20	8

src/codegen/isel.rsmodified

          // Slow path (unfused): the condition is an arbitrary boolean in a
          // register. Materialize with `CMP cond, #0; CSEL dest, tv, fv, NE`.
          InstKind::Select(cond, tv, fv) => {
 -            let true_reg = ctx.lookup_vreg(*tv);
 -            let false_reg = ctx.lookup_vreg(*fv);
              let class = type_to_reg_class(&inst.ty);
              let dest = ctx.get_vreg(mf, inst.id, class);
 +            let true_reg = coerce_select_operand_vreg(mf, ctx, mb, func, *tv, &inst.ty);
 +            let false_reg = coerce_select_operand_vreg(mf, ctx, mb, func, *fv, &inst.ty);
              let arm_cond = if let Some(&fused_cond) = ctx.fused_arm_cond.get(cond) {
                  // Flags already set by the fused CMP — no extra compare needed.
      dest
+ }
 +fn machine_vreg_class(mf: &MachineFunction, vreg: VRegId) -> RegClass {
 +    mf.vregs
 +        .iter()
 +        .find(|r| r.id == vreg)
 +        .map(|r| r.class)
 +        .expect("isel: vreg not registered")
 +}
++
 +fn coerce_select_operand_vreg(
 +    mf: &mut MachineFunction,
 +    ctx: &mut ISelCtx,
 +    mb: MBlockId,
 +    func: &Function,
 +    value: ValueId,
 +    target_ty: &IrType,
 +) -> VRegId {
 +    let src = ctx.lookup_vreg(value);
 +    let src_class = machine_vreg_class(mf, src);
 +    let target_class = type_to_reg_class(target_ty);
 +    if src_class == target_class {
 +        return src;
 +    }
++
 +    let dest = mf.new_vreg(target_class);
 +    let src_ty = func.value_type(value);
 +    let opcode = match (src_class, target_class) {
 +        (RegClass::Gp32, RegClass::Gp64) => {
 +            if matches!(target_ty, IrType::Ptr(_) | IrType::FuncPtr(_))
 +                || zero_extend_cmp_type(src_ty.as_ref())
 +            {
 +                ArmOpcode::MovReg
 +            } else {
 +                match src_ty.as_ref() {
 +                    Some(IrType::Int(IntWidth::I8)) => ArmOpcode::Sxtb,
 +                    Some(IrType::Int(IntWidth::I16)) => ArmOpcode::Sxth,
 +                    Some(IrType::Int(IntWidth::I32)) | Some(IrType::Bool) => ArmOpcode::Sxtw,
 +                    _ => ArmOpcode::MovReg,
 +                }
 +            }
 +        }
 +        (RegClass::Gp64, RegClass::Gp32) => ArmOpcode::MovReg,
 +        (RegClass::Fp32, RegClass::Fp64) => ArmOpcode::FcvtDS,
 +        (RegClass::Fp64, RegClass::Fp32) => ArmOpcode::FcvtSD,
 +        _ => ArmOpcode::MovReg,
 +    };
++
 +    mf.block_mut(mb).insts.push(MachineInst {
 +        opcode,
 +        operands: vec![MachineOperand::VReg(dest), MachineOperand::VReg(src)],
 +        def: Some(dest),
 +    });
 +    dest
 +}
++
  fn int_width_class(w: &IntWidth) -> RegClass {
      match w {
          IntWidth::I64 => RegClass::Gp64,
          );
+     }
 +    #[test]
 +    fn select_coerces_mixed_gp_widths_before_csel() {
 +        let mf = select_simple(|b| {
 +            let cond = b.const_bool(true);
 +            let wide = b.const_i64(7);
 +            let narrow = b.const_i32(-1);
 +            let _s = b.select(cond, wide, narrow);
 +            b.ret_void();
 +        });
 +        let csel = mf.blocks[0]
 +            .insts
 +            .iter()
 +            .find(|i| i.opcode == ArmOpcode::CselReg)
 +            .expect("expected CSEL for mixed-width select");
 +        for operand in csel.operands.iter().take(3) {
 +            let MachineOperand::VReg(vreg) = operand else {
 +                continue;
 +            };
 +            assert_eq!(
 +                machine_vreg_class(&mf, *vreg),
 +                RegClass::Gp64,
 +                "mixed-width select operands should be coerced to the result width before CSEL"
 +            );
 +        }
 +    }
++
      #[test]
      fn csel_fusion_eliminates_cset_and_extra_cmp() {
          // ICmp used solely by a Select → CSET and CMP cond, #0 must NOT appear.

tests/i128_stack_args.rsmodified

+     }
+ }
 +fn assert_i128_return_stored_after_call(asm: &str, call_marker: &str, context: &str) {
 +    let call_idx = asm
 +        .find(call_marker)
 +        .unwrap_or_else(|| panic!("missing call marker '{}' in:\n{}", call_marker, asm));
 +    assert!(
 +        asm[call_idx..].contains("stp x0, x1, [x29, #-"),
 +        "{}:\n{}",
 +        context,
 +        asm
 +    );
 +}
++
  #[test]
  fn internal_i128_stack_call_spills_fifth_arg_and_loads_incoming_slot_at_o0() {
      let asm = capture_text(
          "callee should load the incoming stack-passed integer(16) arg from [x29, #16]:\n{}",
          asm
      );
 -    assert!(
 -        asm.contains("stp x0, x1, [x29, #-360]"),
 -        "caller should still receive the returned integer(16) value in x0/x1 even when args spill to the stack:\n{}",
 -        asm
 +    assert_i128_return_stored_after_call(
 +        &asm,
 +        "bl _afs_internal_",
 +        "caller should still receive the returned integer(16) value in x0/x1 even when args spill to the stack",
      );
+ }
          "fifth external integer(16) arg should spill to the outgoing stack area:\n{}",
          asm
      );
 -    assert!(
 -        asm.contains("stp x0, x1, [x29, #-360]"),
 -        "external integer(16) stack-call should still receive the returned value in x0/x1:\n{}",
 -        asm
 +    assert_i128_return_stored_after_call(
 +        &asm,
 +        "bl _add5_ext",
 +        "external integer(16) stack-call should still receive the returned value in x0/x1",
      );
+ }