`784a9e1`

Mirror driver pipeline in testing.rs (peephole/parallelize/split-bridges/relax-branches)

Authored by mfwolffe <wolffemf@dukes.jmu.edu> 1 week ago

Status	File	+	-
M	`src/testing.rs`	18	0

src/testing.rsmodified

+     }
      let mut allocated = machine_funcs.clone();
 +    // Backend peephole at O2+ (must run BEFORE regalloc — it
 +    // operates on vregs).
 +    if request.opt_level >= OptLevel::O2 {
 +        for mf in &mut allocated {
 +            crate::codegen::peephole::run_peephole(mf);
 +        }
 +    }
      for mf in &mut allocated {
          let liveness = crate::codegen::liveness::compute_liveness(mf);
          let result = linearscan::linear_scan(mf);
          linearscan::apply_allocation(mf, &result, &liveness);
 +        // Post-allocation passes — must mirror the driver pipeline so
 +        // captured asm matches the binary the user actually ships.
 +        // parallelize_call_arg_moves in particular fixes a w0/w1
 +        // clobber pattern visible at high register pressure.
 +        linearscan::parallelize_entry_arg_moves(mf);
 +        linearscan::parallelize_call_arg_moves(mf);
 +        linearscan::insert_split_bridges(mf, &result.split_records);
          linearscan::insert_callee_saves(mf, &result.callee_saved_used);
          linearscan::coalesce_moves(mf);
 +        if request.opt_level >= OptLevel::O1 {
 +            crate::codegen::tailcall::tail_call_opt(mf);
 +        }
 +        crate::codegen::relax_branches::relax_branches(mf);
+     }
      if wants(Stage::Regalloc) {
          stages.insert(