| 1 | //! Integration tests that verify our encodings against the system assembler. |
| 2 | //! |
| 3 | //! For each test, we: |
| 4 | //! 1. Write an assembly instruction to a temp .s file |
| 5 | //! 2. Assemble it with Apple `as` |
| 6 | //! 3. Extract the 4-byte encoding from the .o with `otool -t` |
| 7 | //! 4. Compare against our encode() output |
| 8 | //! |
| 9 | //! This gives us ground-truth validation: if Apple `as` and our encoder |
| 10 | //! agree on every instruction, our encoder is correct. |
| 11 | |
| 12 | use std::io::Write; |
| 13 | use std::process::Command; |
| 14 | |
| 15 | use afs_as::encode::{AddrExtend, BarrierOpt, Inst, RegExtend, RegShift}; |
| 16 | use afs_as::reg::*; |
| 17 | |
| 18 | /// Assemble a single ARM64 instruction with Apple `as` and return its 4-byte encoding. |
| 19 | fn system_encode(asm: &str) -> u32 { |
| 20 | use std::sync::atomic::{AtomicU64, Ordering}; |
| 21 | static COUNTER: AtomicU64 = AtomicU64::new(0); |
| 22 | let id = COUNTER.fetch_add(1, Ordering::Relaxed); |
| 23 | let pid = std::process::id(); |
| 24 | let tid = std::thread::current().id(); |
| 25 | let dir = std::env::temp_dir(); |
| 26 | let s_path = dir.join(format!("afs_as_test_{}_{:?}_{}.s", pid, tid, id)); |
| 27 | let o_path = dir.join(format!("afs_as_test_{}_{:?}_{}.o", pid, tid, id)); |
| 28 | |
| 29 | // Write assembly file |
| 30 | let mut f = std::fs::File::create(&s_path).expect("create .s"); |
| 31 | writeln!(f, ".text\n{}", asm).expect("write .s"); |
| 32 | drop(f); |
| 33 | |
| 34 | // Assemble |
| 35 | let status = Command::new("as") |
| 36 | .args(["-o", o_path.to_str().unwrap(), s_path.to_str().unwrap()]) |
| 37 | .status() |
| 38 | .expect("run as"); |
| 39 | assert!(status.success(), "as failed for: {}", asm); |
| 40 | |
| 41 | // Extract encoding with otool |
| 42 | let output = Command::new("otool") |
| 43 | .args(["-t", o_path.to_str().unwrap()]) |
| 44 | .output() |
| 45 | .expect("run otool"); |
| 46 | let text = String::from_utf8_lossy(&output.stdout); |
| 47 | |
| 48 | // Parse: otool output has "addr hex hex hex ..." lines after header |
| 49 | // We want the first hex word after the address on the data line |
| 50 | let hex = text |
| 51 | .lines() |
| 52 | .filter(|line| line.starts_with("0")) |
| 53 | .flat_map(|line| line.split_whitespace().skip(1)) |
| 54 | .next() |
| 55 | .unwrap_or_else(|| panic!("no encoding found in otool output for: {}", asm)); |
| 56 | |
| 57 | u32::from_str_radix(hex, 16).unwrap_or_else(|_| panic!("bad hex '{}' for: {}", hex, asm)) |
| 58 | } |
| 59 | |
| 60 | /// Helper: verify that our encoding matches the system assembler. |
| 61 | fn verify(asm: &str, inst: Inst) { |
| 62 | let expected = system_encode(asm); |
| 63 | let got = inst.encode(); |
| 64 | assert_eq!( |
| 65 | got, expected, |
| 66 | "\nMismatch for: {}\n ours: 0x{:08X}\n system: 0x{:08X}", |
| 67 | asm, got, expected |
| 68 | ); |
| 69 | } |
| 70 | |
| 71 | // ---- Data processing ---- |
| 72 | |
| 73 | #[test] |
| 74 | fn sys_add_reg() { |
| 75 | verify( |
| 76 | "add x5, x6, x7", |
| 77 | Inst::AddReg { |
| 78 | rd: X5, |
| 79 | rn: X6, |
| 80 | rm: X7, |
| 81 | sf: true, |
| 82 | }, |
| 83 | ); |
| 84 | } |
| 85 | #[test] |
| 86 | fn sys_sub_reg() { |
| 87 | verify( |
| 88 | "sub x10, x11, x12", |
| 89 | Inst::SubReg { |
| 90 | rd: X10, |
| 91 | rn: X11, |
| 92 | rm: X12, |
| 93 | sf: true, |
| 94 | }, |
| 95 | ); |
| 96 | } |
| 97 | #[test] |
| 98 | fn sys_add_w() { |
| 99 | verify( |
| 100 | "add w3, w4, w5", |
| 101 | Inst::AddReg { |
| 102 | rd: W3, |
| 103 | rn: W4, |
| 104 | rm: W5, |
| 105 | sf: false, |
| 106 | }, |
| 107 | ); |
| 108 | } |
| 109 | #[test] |
| 110 | fn sys_add_shift_reg() { |
| 111 | verify( |
| 112 | "add x0, x1, x2, lsl #3", |
| 113 | Inst::AddShiftReg { |
| 114 | rd: X0, |
| 115 | rn: X1, |
| 116 | rm: X2, |
| 117 | shift: RegShift::Lsl, |
| 118 | amount: 3, |
| 119 | sf: true, |
| 120 | }, |
| 121 | ); |
| 122 | } |
| 123 | #[test] |
| 124 | fn sys_sub_shift_reg() { |
| 125 | verify( |
| 126 | "sub w3, w4, w5, asr #7", |
| 127 | Inst::SubShiftReg { |
| 128 | rd: W3, |
| 129 | rn: W4, |
| 130 | rm: W5, |
| 131 | shift: RegShift::Asr, |
| 132 | amount: 7, |
| 133 | sf: false, |
| 134 | }, |
| 135 | ); |
| 136 | } |
| 137 | #[test] |
| 138 | fn sys_cmp_shift_reg() { |
| 139 | verify( |
| 140 | "cmp x6, x7, lsr #4", |
| 141 | Inst::SubsShiftReg { |
| 142 | rd: XZR, |
| 143 | rn: X6, |
| 144 | rm: X7, |
| 145 | shift: RegShift::Lsr, |
| 146 | amount: 4, |
| 147 | sf: true, |
| 148 | }, |
| 149 | ); |
| 150 | } |
| 151 | #[test] |
| 152 | fn sys_add_ext_reg() { |
| 153 | verify( |
| 154 | "add x0, x0, w1, sxtw #3", |
| 155 | Inst::AddExtReg { |
| 156 | rd: X0, |
| 157 | rn: X0, |
| 158 | rm: W1, |
| 159 | extend: RegExtend::Sxtw, |
| 160 | amount: 3, |
| 161 | sf: true, |
| 162 | }, |
| 163 | ); |
| 164 | } |
| 165 | #[test] |
| 166 | fn sys_add_ext_reg_sp_base() { |
| 167 | verify( |
| 168 | "add x11, sp, w12, sxtw #2", |
| 169 | Inst::AddExtReg { |
| 170 | rd: X11, |
| 171 | rn: SP, |
| 172 | rm: W12, |
| 173 | extend: RegExtend::Sxtw, |
| 174 | amount: 2, |
| 175 | sf: true, |
| 176 | }, |
| 177 | ); |
| 178 | } |
| 179 | #[test] |
| 180 | fn sys_sub_ext_reg() { |
| 181 | verify( |
| 182 | "sub x2, x3, w4, uxtw #2", |
| 183 | Inst::SubExtReg { |
| 184 | rd: X2, |
| 185 | rn: X3, |
| 186 | rm: W4, |
| 187 | extend: RegExtend::Uxtw, |
| 188 | amount: 2, |
| 189 | sf: true, |
| 190 | }, |
| 191 | ); |
| 192 | } |
| 193 | #[test] |
| 194 | fn sys_cmp_ext_reg() { |
| 195 | verify( |
| 196 | "cmp x0, w1, sxtw", |
| 197 | Inst::SubsExtReg { |
| 198 | rd: XZR, |
| 199 | rn: X0, |
| 200 | rm: W1, |
| 201 | extend: RegExtend::Sxtw, |
| 202 | amount: 0, |
| 203 | sf: true, |
| 204 | }, |
| 205 | ); |
| 206 | } |
| 207 | #[test] |
| 208 | fn sys_mul() { |
| 209 | verify( |
| 210 | "mul x0, x1, x2", |
| 211 | Inst::Mul { |
| 212 | rd: X0, |
| 213 | rn: X1, |
| 214 | rm: X2, |
| 215 | sf: true, |
| 216 | }, |
| 217 | ); |
| 218 | } |
| 219 | #[test] |
| 220 | fn sys_madd() { |
| 221 | verify( |
| 222 | "madd w0, w0, w0, w8", |
| 223 | Inst::Madd { |
| 224 | rd: W0, |
| 225 | rn: W0, |
| 226 | rm: W0, |
| 227 | ra: W8, |
| 228 | sf: false, |
| 229 | }, |
| 230 | ); |
| 231 | } |
| 232 | #[test] |
| 233 | fn sys_msub() { |
| 234 | verify( |
| 235 | "msub w9, w8, w1, w0", |
| 236 | Inst::Msub { |
| 237 | rd: W9, |
| 238 | rn: W8, |
| 239 | rm: W1, |
| 240 | ra: W0, |
| 241 | sf: false, |
| 242 | }, |
| 243 | ); |
| 244 | } |
| 245 | #[test] |
| 246 | fn sys_umull() { |
| 247 | verify( |
| 248 | "umull x9, w8, w9", |
| 249 | Inst::Umull { |
| 250 | rd: X9, |
| 251 | rn: W8, |
| 252 | rm: W9, |
| 253 | }, |
| 254 | ); |
| 255 | } |
| 256 | #[test] |
| 257 | fn sys_sdiv() { |
| 258 | verify( |
| 259 | "sdiv x3, x4, x5", |
| 260 | Inst::Sdiv { |
| 261 | rd: X3, |
| 262 | rn: X4, |
| 263 | rm: X5, |
| 264 | sf: true, |
| 265 | }, |
| 266 | ); |
| 267 | } |
| 268 | #[test] |
| 269 | fn sys_udiv() { |
| 270 | verify( |
| 271 | "udiv x3, x4, x5", |
| 272 | Inst::Udiv { |
| 273 | rd: X3, |
| 274 | rn: X4, |
| 275 | rm: X5, |
| 276 | sf: true, |
| 277 | }, |
| 278 | ); |
| 279 | } |
| 280 | #[test] |
| 281 | fn sys_and() { |
| 282 | verify( |
| 283 | "and x3, x4, x5", |
| 284 | Inst::AndReg { |
| 285 | rd: X3, |
| 286 | rn: X4, |
| 287 | rm: X5, |
| 288 | sf: true, |
| 289 | }, |
| 290 | ); |
| 291 | } |
| 292 | #[test] |
| 293 | fn sys_and_imm() { |
| 294 | verify( |
| 295 | "and w8, w8, #0x7", |
| 296 | Inst::AndImm { |
| 297 | rd: W8, |
| 298 | rn: W8, |
| 299 | imm: 0x7, |
| 300 | sf: false, |
| 301 | }, |
| 302 | ); |
| 303 | } |
| 304 | #[test] |
| 305 | fn sys_orr() { |
| 306 | verify( |
| 307 | "orr x3, x4, x5", |
| 308 | Inst::OrrReg { |
| 309 | rd: X3, |
| 310 | rn: X4, |
| 311 | rm: X5, |
| 312 | sf: true, |
| 313 | }, |
| 314 | ); |
| 315 | } |
| 316 | #[test] |
| 317 | fn sys_orn() { |
| 318 | verify( |
| 319 | "orn x3, x4, x5", |
| 320 | Inst::OrnReg { |
| 321 | rd: X3, |
| 322 | rn: X4, |
| 323 | rm: X5, |
| 324 | sf: true, |
| 325 | }, |
| 326 | ); |
| 327 | } |
| 328 | #[test] |
| 329 | fn sys_eor() { |
| 330 | verify( |
| 331 | "eor x3, x4, x5", |
| 332 | Inst::EorReg { |
| 333 | rd: X3, |
| 334 | rn: X4, |
| 335 | rm: X5, |
| 336 | sf: true, |
| 337 | }, |
| 338 | ); |
| 339 | } |
| 340 | |
| 341 | // ---- Data processing (immediate) ---- |
| 342 | |
| 343 | #[test] |
| 344 | fn sys_add_imm() { |
| 345 | verify( |
| 346 | "add x3, x4, #100", |
| 347 | Inst::AddImm { |
| 348 | rd: X3, |
| 349 | rn: X4, |
| 350 | imm12: 100, |
| 351 | shift: false, |
| 352 | sf: true, |
| 353 | }, |
| 354 | ); |
| 355 | } |
| 356 | #[test] |
| 357 | fn sys_sub_imm() { |
| 358 | verify( |
| 359 | "sub x3, x4, #100", |
| 360 | Inst::SubImm { |
| 361 | rd: X3, |
| 362 | rn: X4, |
| 363 | imm12: 100, |
| 364 | shift: false, |
| 365 | sf: true, |
| 366 | }, |
| 367 | ); |
| 368 | } |
| 369 | #[test] |
| 370 | fn sys_cmp_imm() { |
| 371 | verify( |
| 372 | "cmp x5, #255", |
| 373 | Inst::SubsImm { |
| 374 | rd: XZR, |
| 375 | rn: X5, |
| 376 | imm12: 255, |
| 377 | shift: false, |
| 378 | sf: true, |
| 379 | }, |
| 380 | ); |
| 381 | } |
| 382 | |
| 383 | // ---- Move ---- |
| 384 | |
| 385 | #[test] |
| 386 | fn sys_movz() { |
| 387 | verify( |
| 388 | "movz x8, #0xBEEF", |
| 389 | Inst::Movz { |
| 390 | rd: X8, |
| 391 | imm16: 0xBEEF, |
| 392 | shift: 0, |
| 393 | sf: true, |
| 394 | }, |
| 395 | ); |
| 396 | } |
| 397 | #[test] |
| 398 | fn sys_movz_hi() { |
| 399 | verify( |
| 400 | "movz x8, #0xCAFE, lsl #48", |
| 401 | Inst::Movz { |
| 402 | rd: X8, |
| 403 | imm16: 0xCAFE, |
| 404 | shift: 48, |
| 405 | sf: true, |
| 406 | }, |
| 407 | ); |
| 408 | } |
| 409 | #[test] |
| 410 | fn sys_movk() { |
| 411 | verify( |
| 412 | "movk x9, #0x1234, lsl #16", |
| 413 | Inst::Movk { |
| 414 | rd: X9, |
| 415 | imm16: 0x1234, |
| 416 | shift: 16, |
| 417 | sf: true, |
| 418 | }, |
| 419 | ); |
| 420 | } |
| 421 | #[test] |
| 422 | fn sys_movn_hi() { |
| 423 | verify( |
| 424 | "movn x0, #1, lsl #16", |
| 425 | Inst::Movn { |
| 426 | rd: X0, |
| 427 | imm16: 1, |
| 428 | shift: 16, |
| 429 | sf: true, |
| 430 | }, |
| 431 | ); |
| 432 | } |
| 433 | |
| 434 | #[test] |
| 435 | fn sys_mov_wzr() { |
| 436 | verify( |
| 437 | "mov w26, wzr", |
| 438 | Inst::OrrReg { |
| 439 | rd: W26, |
| 440 | rn: WZR, |
| 441 | rm: WZR, |
| 442 | sf: false, |
| 443 | }, |
| 444 | ); |
| 445 | } |
| 446 | |
| 447 | // ---- Shifts ---- |
| 448 | |
| 449 | #[test] |
| 450 | fn sys_lsl() { |
| 451 | verify( |
| 452 | "lsl x0, x1, #7", |
| 453 | Inst::LslImm { |
| 454 | rd: X0, |
| 455 | rn: X1, |
| 456 | amount: 7, |
| 457 | sf: true, |
| 458 | }, |
| 459 | ); |
| 460 | } |
| 461 | #[test] |
| 462 | fn sys_lsr() { |
| 463 | verify( |
| 464 | "lsr x0, x1, #15", |
| 465 | Inst::LsrImm { |
| 466 | rd: X0, |
| 467 | rn: X1, |
| 468 | amount: 15, |
| 469 | sf: true, |
| 470 | }, |
| 471 | ); |
| 472 | } |
| 473 | #[test] |
| 474 | fn sys_asr() { |
| 475 | verify( |
| 476 | "asr x0, x1, #31", |
| 477 | Inst::AsrImm { |
| 478 | rd: X0, |
| 479 | rn: X1, |
| 480 | amount: 31, |
| 481 | sf: true, |
| 482 | }, |
| 483 | ); |
| 484 | } |
| 485 | |
| 486 | // ---- Branches ---- |
| 487 | |
| 488 | #[test] |
| 489 | fn sys_b() { |
| 490 | verify("b #20", Inst::B { offset: 20 }); |
| 491 | } |
| 492 | #[test] |
| 493 | fn sys_bl() { |
| 494 | verify("bl #40", Inst::Bl { offset: 40 }); |
| 495 | } |
| 496 | #[test] |
| 497 | fn sys_b_eq() { |
| 498 | verify( |
| 499 | "b.eq #24", |
| 500 | Inst::BCond { |
| 501 | cond: Cond::EQ, |
| 502 | offset: 24, |
| 503 | }, |
| 504 | ); |
| 505 | } |
| 506 | #[test] |
| 507 | fn sys_b_lt() { |
| 508 | verify( |
| 509 | "b.lt #32", |
| 510 | Inst::BCond { |
| 511 | cond: Cond::LT, |
| 512 | offset: 32, |
| 513 | }, |
| 514 | ); |
| 515 | } |
| 516 | #[test] |
| 517 | fn sys_cbz() { |
| 518 | verify( |
| 519 | "cbz x5, #16", |
| 520 | Inst::Cbz { |
| 521 | rt: X5, |
| 522 | offset: 16, |
| 523 | sf: true, |
| 524 | }, |
| 525 | ); |
| 526 | } |
| 527 | #[test] |
| 528 | fn sys_cbnz() { |
| 529 | verify( |
| 530 | "cbnz x10, #24", |
| 531 | Inst::Cbnz { |
| 532 | rt: X10, |
| 533 | offset: 24, |
| 534 | sf: true, |
| 535 | }, |
| 536 | ); |
| 537 | } |
| 538 | #[test] |
| 539 | fn sys_tbz() { |
| 540 | verify( |
| 541 | "tbz x0, #5, #8", |
| 542 | Inst::Tbz { |
| 543 | rt: X0, |
| 544 | bit: 5, |
| 545 | offset: 8, |
| 546 | sf: true, |
| 547 | }, |
| 548 | ); |
| 549 | } |
| 550 | #[test] |
| 551 | fn sys_tbnz() { |
| 552 | verify( |
| 553 | "tbnz x1, #33, #12", |
| 554 | Inst::Tbnz { |
| 555 | rt: X1, |
| 556 | bit: 33, |
| 557 | offset: 12, |
| 558 | sf: true, |
| 559 | }, |
| 560 | ); |
| 561 | } |
| 562 | #[test] |
| 563 | fn sys_ret() { |
| 564 | verify("ret", Inst::Ret { rn: X30 }); |
| 565 | } |
| 566 | #[test] |
| 567 | fn sys_br() { |
| 568 | verify("br x8", Inst::Br { rn: X8 }); |
| 569 | } |
| 570 | #[test] |
| 571 | fn sys_blr() { |
| 572 | verify("blr x9", Inst::Blr { rn: X9 }); |
| 573 | } |
| 574 | #[test] |
| 575 | fn sys_csel() { |
| 576 | verify( |
| 577 | "csel w0, w0, w1, gt", |
| 578 | Inst::Csel { |
| 579 | rd: W0, |
| 580 | rn: W0, |
| 581 | rm: W1, |
| 582 | cond: Cond::GT, |
| 583 | sf: false, |
| 584 | }, |
| 585 | ); |
| 586 | } |
| 587 | #[test] |
| 588 | fn sys_ccmp() { |
| 589 | verify( |
| 590 | "ccmp w0, #3, #4, ne", |
| 591 | Inst::CcmpImm { |
| 592 | rn: W0, |
| 593 | imm5: 3, |
| 594 | nzcv: 4, |
| 595 | cond: Cond::NE, |
| 596 | sf: false, |
| 597 | }, |
| 598 | ); |
| 599 | } |
| 600 | #[test] |
| 601 | fn sys_ccmn() { |
| 602 | verify( |
| 603 | "ccmn x3, #9, #1, ge", |
| 604 | Inst::CcmnImm { |
| 605 | rn: X3, |
| 606 | imm5: 9, |
| 607 | nzcv: 1, |
| 608 | cond: Cond::GE, |
| 609 | sf: true, |
| 610 | }, |
| 611 | ); |
| 612 | } |
| 613 | #[test] |
| 614 | fn sys_csinc() { |
| 615 | verify( |
| 616 | "csinc x2, x3, x3, ne", |
| 617 | Inst::Csinc { |
| 618 | rd: X2, |
| 619 | rn: X3, |
| 620 | rm: X3, |
| 621 | cond: Cond::NE, |
| 622 | sf: true, |
| 623 | }, |
| 624 | ); |
| 625 | } |
| 626 | #[test] |
| 627 | fn sys_csinv() { |
| 628 | verify( |
| 629 | "csinv x2, x3, x4, ne", |
| 630 | Inst::Csinv { |
| 631 | rd: X2, |
| 632 | rn: X3, |
| 633 | rm: X4, |
| 634 | cond: Cond::NE, |
| 635 | sf: true, |
| 636 | }, |
| 637 | ); |
| 638 | } |
| 639 | #[test] |
| 640 | fn sys_csneg() { |
| 641 | verify( |
| 642 | "csneg x5, x6, x7, gt", |
| 643 | Inst::Csneg { |
| 644 | rd: X5, |
| 645 | rn: X6, |
| 646 | rm: X7, |
| 647 | cond: Cond::GT, |
| 648 | sf: true, |
| 649 | }, |
| 650 | ); |
| 651 | } |
| 652 | #[test] |
| 653 | fn sys_csetm() { |
| 654 | verify( |
| 655 | "csetm w8, eq", |
| 656 | Inst::Csinv { |
| 657 | rd: W8, |
| 658 | rn: XZR, |
| 659 | rm: XZR, |
| 660 | cond: Cond::NE, |
| 661 | sf: false, |
| 662 | }, |
| 663 | ); |
| 664 | } |
| 665 | #[test] |
| 666 | fn sys_cinv() { |
| 667 | verify( |
| 668 | "cinv w9, w10, mi", |
| 669 | Inst::Csinv { |
| 670 | rd: W9, |
| 671 | rn: W10, |
| 672 | rm: W10, |
| 673 | cond: Cond::PL, |
| 674 | sf: false, |
| 675 | }, |
| 676 | ); |
| 677 | } |
| 678 | #[test] |
| 679 | fn sys_cneg() { |
| 680 | verify( |
| 681 | "cneg x11, x12, lt", |
| 682 | Inst::Csneg { |
| 683 | rd: X11, |
| 684 | rn: X12, |
| 685 | rm: X12, |
| 686 | cond: Cond::GE, |
| 687 | sf: true, |
| 688 | }, |
| 689 | ); |
| 690 | } |
| 691 | #[test] |
| 692 | fn sys_tst_imm() { |
| 693 | verify( |
| 694 | "tst w8, #0x7", |
| 695 | Inst::AndsImm { |
| 696 | rd: XZR, |
| 697 | rn: W8, |
| 698 | imm: 0x7, |
| 699 | sf: false, |
| 700 | }, |
| 701 | ); |
| 702 | } |
| 703 | #[test] |
| 704 | fn sys_ubfiz() { |
| 705 | verify( |
| 706 | "ubfiz w8, w0, #5, #3", |
| 707 | Inst::Ubfiz { |
| 708 | rd: W8, |
| 709 | rn: W0, |
| 710 | lsb: 5, |
| 711 | width: 3, |
| 712 | sf: false, |
| 713 | }, |
| 714 | ); |
| 715 | } |
| 716 | #[test] |
| 717 | fn sys_bfi() { |
| 718 | verify( |
| 719 | "bfi w0, w8, #5, #27", |
| 720 | Inst::Bfi { |
| 721 | rd: W0, |
| 722 | rn: W8, |
| 723 | lsb: 5, |
| 724 | width: 27, |
| 725 | sf: false, |
| 726 | }, |
| 727 | ); |
| 728 | } |
| 729 | #[test] |
| 730 | fn sys_bfxil() { |
| 731 | verify( |
| 732 | "bfxil w8, w0, #3, #5", |
| 733 | Inst::Bfxil { |
| 734 | rd: W8, |
| 735 | rn: W0, |
| 736 | lsb: 3, |
| 737 | width: 5, |
| 738 | sf: false, |
| 739 | }, |
| 740 | ); |
| 741 | } |
| 742 | |
| 743 | // ---- Load/Store (unsigned offset) ---- |
| 744 | |
| 745 | #[test] |
| 746 | fn sys_ldr64() { |
| 747 | verify( |
| 748 | "ldr x3, [x4, #24]", |
| 749 | Inst::LdrImm64 { |
| 750 | rt: X3, |
| 751 | rn: X4, |
| 752 | offset: 24, |
| 753 | }, |
| 754 | ); |
| 755 | } |
| 756 | #[test] |
| 757 | fn sys_str64() { |
| 758 | verify( |
| 759 | "str x3, [x4, #32]", |
| 760 | Inst::StrImm64 { |
| 761 | rt: X3, |
| 762 | rn: X4, |
| 763 | offset: 32, |
| 764 | }, |
| 765 | ); |
| 766 | } |
| 767 | #[test] |
| 768 | fn sys_ldr32() { |
| 769 | verify( |
| 770 | "ldr w3, [x4, #12]", |
| 771 | Inst::LdrImm32 { |
| 772 | rt: W3, |
| 773 | rn: X4, |
| 774 | offset: 12, |
| 775 | }, |
| 776 | ); |
| 777 | } |
| 778 | #[test] |
| 779 | fn sys_str32() { |
| 780 | verify( |
| 781 | "str w3, [x4, #16]", |
| 782 | Inst::StrImm32 { |
| 783 | rt: W3, |
| 784 | rn: X4, |
| 785 | offset: 16, |
| 786 | }, |
| 787 | ); |
| 788 | } |
| 789 | #[test] |
| 790 | fn sys_ldur64() { |
| 791 | verify( |
| 792 | "ldur x9, [x29, #-8]", |
| 793 | Inst::Ldur64 { |
| 794 | rt: X9, |
| 795 | rn: X29, |
| 796 | offset: -8, |
| 797 | }, |
| 798 | ); |
| 799 | } |
| 800 | #[test] |
| 801 | fn sys_stur32() { |
| 802 | verify( |
| 803 | "stur w6, [x7, #-4]", |
| 804 | Inst::Stur32 { |
| 805 | rt: W6, |
| 806 | rn: X7, |
| 807 | offset: -4, |
| 808 | }, |
| 809 | ); |
| 810 | } |
| 811 | #[test] |
| 812 | fn sys_ldr_negative_alias() { |
| 813 | verify( |
| 814 | "ldr x0, [x1, #-8]", |
| 815 | Inst::Ldur64 { |
| 816 | rt: X0, |
| 817 | rn: X1, |
| 818 | offset: -8, |
| 819 | }, |
| 820 | ); |
| 821 | } |
| 822 | #[test] |
| 823 | fn sys_ldr_post32() { |
| 824 | verify( |
| 825 | "ldr w0, [x1], #4", |
| 826 | Inst::LdrPost32 { |
| 827 | rt: W0, |
| 828 | rn: X1, |
| 829 | offset: 4, |
| 830 | }, |
| 831 | ); |
| 832 | } |
| 833 | #[test] |
| 834 | fn sys_str_pre32() { |
| 835 | verify( |
| 836 | "str w2, [x3, #-4]!", |
| 837 | Inst::StrPre32 { |
| 838 | rt: W2, |
| 839 | rn: X3, |
| 840 | offset: -4, |
| 841 | }, |
| 842 | ); |
| 843 | } |
| 844 | #[test] |
| 845 | fn sys_ldr64_tlvp_pageoff() { |
| 846 | verify( |
| 847 | "ldr x0, [x0, _tls_counter@TLVPPAGEOFF]", |
| 848 | Inst::LdrImm64 { |
| 849 | rt: X0, |
| 850 | rn: X0, |
| 851 | offset: 0, |
| 852 | }, |
| 853 | ); |
| 854 | } |
| 855 | #[test] |
| 856 | fn sys_ldr_lit64() { |
| 857 | verify("ldr x0, #8", Inst::LdrLit64 { rt: X0, offset: 8 }); |
| 858 | } |
| 859 | #[test] |
| 860 | fn sys_ldr_lit32() { |
| 861 | verify("ldr w1, #12", Inst::LdrLit32 { rt: W1, offset: 12 }); |
| 862 | } |
| 863 | #[test] |
| 864 | fn sys_ldr64_reg() { |
| 865 | verify( |
| 866 | "ldr x0, [x1, x2]", |
| 867 | Inst::LdrReg64 { |
| 868 | rt: X0, |
| 869 | rn: X1, |
| 870 | rm: X2, |
| 871 | extend: AddrExtend::Lsl, |
| 872 | shift: false, |
| 873 | }, |
| 874 | ); |
| 875 | } |
| 876 | #[test] |
| 877 | fn sys_ldr64_reg_uxtw() { |
| 878 | verify( |
| 879 | "ldr x6, [x7, w8, uxtw #3]", |
| 880 | Inst::LdrReg64 { |
| 881 | rt: X6, |
| 882 | rn: X7, |
| 883 | rm: W8, |
| 884 | extend: AddrExtend::Uxtw, |
| 885 | shift: true, |
| 886 | }, |
| 887 | ); |
| 888 | } |
| 889 | #[test] |
| 890 | fn sys_str64_reg() { |
| 891 | verify( |
| 892 | "str x12, [x13, x14]", |
| 893 | Inst::StrReg64 { |
| 894 | rt: X12, |
| 895 | rn: X13, |
| 896 | rm: X14, |
| 897 | extend: AddrExtend::Lsl, |
| 898 | shift: false, |
| 899 | }, |
| 900 | ); |
| 901 | } |
| 902 | #[test] |
| 903 | fn sys_ldrb() { |
| 904 | verify( |
| 905 | "ldrb w0, [x1, #3]", |
| 906 | Inst::Ldrb { |
| 907 | rt: W0, |
| 908 | rn: X1, |
| 909 | offset: 3, |
| 910 | }, |
| 911 | ); |
| 912 | } |
| 913 | #[test] |
| 914 | fn sys_ldrsb() { |
| 915 | verify( |
| 916 | "ldrsb w0, [x1, #3]", |
| 917 | Inst::Ldrsb32 { |
| 918 | rt: W0, |
| 919 | rn: X1, |
| 920 | offset: 3, |
| 921 | }, |
| 922 | ); |
| 923 | } |
| 924 | #[test] |
| 925 | fn sys_ldrb_post() { |
| 926 | verify( |
| 927 | "ldrb w9, [x1], #1", |
| 928 | Inst::LdrbPost { |
| 929 | rt: W9, |
| 930 | rn: X1, |
| 931 | offset: 1, |
| 932 | }, |
| 933 | ); |
| 934 | } |
| 935 | #[test] |
| 936 | fn sys_ldrsb_post() { |
| 937 | verify( |
| 938 | "ldrsb x9, [x1], #1", |
| 939 | Inst::LdrsbPost64 { |
| 940 | rt: X9, |
| 941 | rn: X1, |
| 942 | offset: 1, |
| 943 | }, |
| 944 | ); |
| 945 | } |
| 946 | #[test] |
| 947 | fn sys_ldrh() { |
| 948 | verify( |
| 949 | "ldrh w0, [x1, #6]", |
| 950 | Inst::Ldrh { |
| 951 | rt: W0, |
| 952 | rn: X1, |
| 953 | offset: 6, |
| 954 | }, |
| 955 | ); |
| 956 | } |
| 957 | #[test] |
| 958 | fn sys_ldrsh() { |
| 959 | verify( |
| 960 | "ldrsh x0, [x1, #4]", |
| 961 | Inst::Ldrsh64 { |
| 962 | rt: X0, |
| 963 | rn: X1, |
| 964 | offset: 4, |
| 965 | }, |
| 966 | ); |
| 967 | } |
| 968 | #[test] |
| 969 | fn sys_strb() { |
| 970 | verify( |
| 971 | "strb w8, [x9]", |
| 972 | Inst::Strb { |
| 973 | rt: W8, |
| 974 | rn: X9, |
| 975 | offset: 0, |
| 976 | }, |
| 977 | ); |
| 978 | } |
| 979 | #[test] |
| 980 | fn sys_strb_post() { |
| 981 | verify( |
| 982 | "strb w9, [x8], #1", |
| 983 | Inst::StrbPost { |
| 984 | rt: W9, |
| 985 | rn: X8, |
| 986 | offset: 1, |
| 987 | }, |
| 988 | ); |
| 989 | } |
| 990 | #[test] |
| 991 | fn sys_strh_pre() { |
| 992 | verify( |
| 993 | "strh w5, [x6, #2]!", |
| 994 | Inst::StrhPre { |
| 995 | rt: W5, |
| 996 | rn: X6, |
| 997 | offset: 2, |
| 998 | }, |
| 999 | ); |
| 1000 | } |
| 1001 | #[test] |
| 1002 | fn sys_ldrsw() { |
| 1003 | verify( |
| 1004 | "ldrsw x0, [x1, #8]", |
| 1005 | Inst::Ldrsw { |
| 1006 | rt: X0, |
| 1007 | rn: X1, |
| 1008 | offset: 8, |
| 1009 | }, |
| 1010 | ); |
| 1011 | } |
| 1012 | #[test] |
| 1013 | fn sys_ldrh_reg() { |
| 1014 | verify( |
| 1015 | "ldrh w3, [x4, w5, uxtw #1]", |
| 1016 | Inst::LdrhReg { |
| 1017 | rt: W3, |
| 1018 | rn: X4, |
| 1019 | rm: W5, |
| 1020 | extend: AddrExtend::Uxtw, |
| 1021 | shift: true, |
| 1022 | }, |
| 1023 | ); |
| 1024 | } |
| 1025 | #[test] |
| 1026 | fn sys_ldrsh_reg() { |
| 1027 | verify( |
| 1028 | "ldrsh w3, [x4, w5, uxtw #1]", |
| 1029 | Inst::LdrshReg32 { |
| 1030 | rt: W3, |
| 1031 | rn: X4, |
| 1032 | rm: W5, |
| 1033 | extend: AddrExtend::Uxtw, |
| 1034 | shift: true, |
| 1035 | }, |
| 1036 | ); |
| 1037 | } |
| 1038 | #[test] |
| 1039 | fn sys_ldrb_reg() { |
| 1040 | verify( |
| 1041 | "ldrb w0, [x1, x2]", |
| 1042 | Inst::LdrbReg { |
| 1043 | rt: W0, |
| 1044 | rn: X1, |
| 1045 | rm: X2, |
| 1046 | extend: AddrExtend::Lsl, |
| 1047 | shift: false, |
| 1048 | }, |
| 1049 | ); |
| 1050 | } |
| 1051 | #[test] |
| 1052 | fn sys_ldrsw_reg() { |
| 1053 | verify( |
| 1054 | "ldrsw x6, [x7, w8, sxtw #2]", |
| 1055 | Inst::LdrswReg { |
| 1056 | rt: X6, |
| 1057 | rn: X7, |
| 1058 | rm: W8, |
| 1059 | extend: AddrExtend::Sxtw, |
| 1060 | shift: true, |
| 1061 | }, |
| 1062 | ); |
| 1063 | } |
| 1064 | #[test] |
| 1065 | fn sys_ldaprb() { |
| 1066 | verify("ldaprb w0, [x1]", Inst::Ldaprb { rt: W0, rn: X1 }); |
| 1067 | } |
| 1068 | #[test] |
| 1069 | fn sys_ldaprh() { |
| 1070 | verify("ldaprh w2, [x3]", Inst::Ldaprh { rt: W2, rn: X3 }); |
| 1071 | } |
| 1072 | #[test] |
| 1073 | fn sys_ldapr() { |
| 1074 | verify("ldapr w8, [x9]", Inst::Ldapr32 { rt: W8, rn: X9 }); |
| 1075 | } |
| 1076 | #[test] |
| 1077 | fn sys_stlrb() { |
| 1078 | verify("stlrb w4, [x5]", Inst::Stlrb { rt: W4, rn: X5 }); |
| 1079 | } |
| 1080 | #[test] |
| 1081 | fn sys_stlrh() { |
| 1082 | verify("stlrh w6, [x7]", Inst::Stlrh { rt: W6, rn: X7 }); |
| 1083 | } |
| 1084 | #[test] |
| 1085 | fn sys_stlr() { |
| 1086 | verify("stlr x10, [x11]", Inst::Stlr64 { rt: X10, rn: X11 }); |
| 1087 | } |
| 1088 | #[test] |
| 1089 | fn sys_ldaddalb() { |
| 1090 | verify( |
| 1091 | "ldaddalb w0, w1, [x2]", |
| 1092 | Inst::Ldaddalb { |
| 1093 | rs: W0, |
| 1094 | rt: W1, |
| 1095 | rn: X2, |
| 1096 | }, |
| 1097 | ); |
| 1098 | } |
| 1099 | #[test] |
| 1100 | fn sys_ldaddalh() { |
| 1101 | verify( |
| 1102 | "ldaddalh w3, w4, [x5]", |
| 1103 | Inst::Ldaddalh { |
| 1104 | rs: W3, |
| 1105 | rt: W4, |
| 1106 | rn: X5, |
| 1107 | }, |
| 1108 | ); |
| 1109 | } |
| 1110 | #[test] |
| 1111 | fn sys_ldumaxalb() { |
| 1112 | verify( |
| 1113 | "ldumaxalb w0, w1, [x2]", |
| 1114 | Inst::Ldumaxalb { |
| 1115 | rs: W0, |
| 1116 | rt: W1, |
| 1117 | rn: X2, |
| 1118 | }, |
| 1119 | ); |
| 1120 | } |
| 1121 | #[test] |
| 1122 | fn sys_ldumaxalh() { |
| 1123 | verify( |
| 1124 | "ldumaxalh w3, w4, [x5]", |
| 1125 | Inst::Ldumaxalh { |
| 1126 | rs: W3, |
| 1127 | rt: W4, |
| 1128 | rn: X5, |
| 1129 | }, |
| 1130 | ); |
| 1131 | } |
| 1132 | #[test] |
| 1133 | fn sys_ldsmaxalb() { |
| 1134 | verify( |
| 1135 | "ldsmaxalb w18, w19, [x20]", |
| 1136 | Inst::Ldsmaxalb { |
| 1137 | rs: W18, |
| 1138 | rt: W19, |
| 1139 | rn: X20, |
| 1140 | }, |
| 1141 | ); |
| 1142 | } |
| 1143 | #[test] |
| 1144 | fn sys_ldsmaxalh() { |
| 1145 | verify( |
| 1146 | "ldsmaxalh w24, w25, [x26]", |
| 1147 | Inst::Ldsmaxalh { |
| 1148 | rs: W24, |
| 1149 | rt: W25, |
| 1150 | rn: X26, |
| 1151 | }, |
| 1152 | ); |
| 1153 | } |
| 1154 | #[test] |
| 1155 | fn sys_ldaddal() { |
| 1156 | verify( |
| 1157 | "ldaddal w0, w8, [x8]", |
| 1158 | Inst::Ldaddal32 { |
| 1159 | rs: W0, |
| 1160 | rt: W8, |
| 1161 | rn: X8, |
| 1162 | }, |
| 1163 | ); |
| 1164 | } |
| 1165 | #[test] |
| 1166 | fn sys_ldumaxal() { |
| 1167 | verify( |
| 1168 | "ldumaxal x9, x10, [x11]", |
| 1169 | Inst::Ldumaxal64 { |
| 1170 | rs: X9, |
| 1171 | rt: X10, |
| 1172 | rn: X11, |
| 1173 | }, |
| 1174 | ); |
| 1175 | } |
| 1176 | #[test] |
| 1177 | fn sys_ldsmaxal() { |
| 1178 | verify( |
| 1179 | "ldsmaxal w0, w1, [x2]", |
| 1180 | Inst::Ldsmaxal32 { |
| 1181 | rs: W0, |
| 1182 | rt: W1, |
| 1183 | rn: X2, |
| 1184 | }, |
| 1185 | ); |
| 1186 | } |
| 1187 | #[test] |
| 1188 | fn sys_ldsminal() { |
| 1189 | verify( |
| 1190 | "ldsminal x9, x10, [x11]", |
| 1191 | Inst::Ldsminal64 { |
| 1192 | rs: X9, |
| 1193 | rt: X10, |
| 1194 | rn: X11, |
| 1195 | }, |
| 1196 | ); |
| 1197 | } |
| 1198 | #[test] |
| 1199 | fn sys_lduminalb() { |
| 1200 | verify( |
| 1201 | "lduminalb w12, w13, [x14]", |
| 1202 | Inst::Lduminalb { |
| 1203 | rs: W12, |
| 1204 | rt: W13, |
| 1205 | rn: X14, |
| 1206 | }, |
| 1207 | ); |
| 1208 | } |
| 1209 | #[test] |
| 1210 | fn sys_lduminalh() { |
| 1211 | verify( |
| 1212 | "lduminalh w15, w16, [x17]", |
| 1213 | Inst::Lduminalh { |
| 1214 | rs: W15, |
| 1215 | rt: W16, |
| 1216 | rn: X17, |
| 1217 | }, |
| 1218 | ); |
| 1219 | } |
| 1220 | #[test] |
| 1221 | fn sys_ldsminalb() { |
| 1222 | verify( |
| 1223 | "ldsminalb w21, w22, [x23]", |
| 1224 | Inst::Ldsminalb { |
| 1225 | rs: W21, |
| 1226 | rt: W22, |
| 1227 | rn: X23, |
| 1228 | }, |
| 1229 | ); |
| 1230 | } |
| 1231 | #[test] |
| 1232 | fn sys_ldsminalh() { |
| 1233 | verify( |
| 1234 | "ldsminalh w27, w28, [x29]", |
| 1235 | Inst::Ldsminalh { |
| 1236 | rs: W27, |
| 1237 | rt: W28, |
| 1238 | rn: X29, |
| 1239 | }, |
| 1240 | ); |
| 1241 | } |
| 1242 | #[test] |
| 1243 | fn sys_lduminal() { |
| 1244 | verify( |
| 1245 | "lduminal w18, w19, [x20]", |
| 1246 | Inst::Lduminal32 { |
| 1247 | rs: W18, |
| 1248 | rt: W19, |
| 1249 | rn: X20, |
| 1250 | }, |
| 1251 | ); |
| 1252 | } |
| 1253 | #[test] |
| 1254 | fn sys_ldclral() { |
| 1255 | verify( |
| 1256 | "ldclral w12, w13, [x14]", |
| 1257 | Inst::Ldclral32 { |
| 1258 | rs: W12, |
| 1259 | rt: W13, |
| 1260 | rn: X14, |
| 1261 | }, |
| 1262 | ); |
| 1263 | } |
| 1264 | #[test] |
| 1265 | fn sys_ldclralb() { |
| 1266 | verify( |
| 1267 | "ldclralb w6, w7, [x8]", |
| 1268 | Inst::Ldclralb { |
| 1269 | rs: W6, |
| 1270 | rt: W7, |
| 1271 | rn: X8, |
| 1272 | }, |
| 1273 | ); |
| 1274 | } |
| 1275 | #[test] |
| 1276 | fn sys_ldclralh() { |
| 1277 | verify( |
| 1278 | "ldclralh w15, w16, [x17]", |
| 1279 | Inst::Ldclralh { |
| 1280 | rs: W15, |
| 1281 | rt: W16, |
| 1282 | rn: X17, |
| 1283 | }, |
| 1284 | ); |
| 1285 | } |
| 1286 | #[test] |
| 1287 | fn sys_ldeoral() { |
| 1288 | verify( |
| 1289 | "ldeoral x9, x10, [x11]", |
| 1290 | Inst::Ldeoral64 { |
| 1291 | rs: X9, |
| 1292 | rt: X10, |
| 1293 | rn: X11, |
| 1294 | }, |
| 1295 | ); |
| 1296 | } |
| 1297 | #[test] |
| 1298 | fn sys_ldeoralb() { |
| 1299 | verify( |
| 1300 | "ldeoralb w3, w4, [x5]", |
| 1301 | Inst::Ldeoralb { |
| 1302 | rs: W3, |
| 1303 | rt: W4, |
| 1304 | rn: X5, |
| 1305 | }, |
| 1306 | ); |
| 1307 | } |
| 1308 | #[test] |
| 1309 | fn sys_ldeoralh() { |
| 1310 | verify( |
| 1311 | "ldeoralh w12, w13, [x14]", |
| 1312 | Inst::Ldeoralh { |
| 1313 | rs: W12, |
| 1314 | rt: W13, |
| 1315 | rn: X14, |
| 1316 | }, |
| 1317 | ); |
| 1318 | } |
| 1319 | #[test] |
| 1320 | fn sys_ldsetal() { |
| 1321 | verify( |
| 1322 | "ldsetal w0, w1, [x2]", |
| 1323 | Inst::Ldsetal32 { |
| 1324 | rs: W0, |
| 1325 | rt: W1, |
| 1326 | rn: X2, |
| 1327 | }, |
| 1328 | ); |
| 1329 | } |
| 1330 | #[test] |
| 1331 | fn sys_ldsetalb() { |
| 1332 | verify( |
| 1333 | "ldsetalb w0, w1, [x2]", |
| 1334 | Inst::Ldsetalb { |
| 1335 | rs: W0, |
| 1336 | rt: W1, |
| 1337 | rn: X2, |
| 1338 | }, |
| 1339 | ); |
| 1340 | } |
| 1341 | #[test] |
| 1342 | fn sys_ldsetalh() { |
| 1343 | verify( |
| 1344 | "ldsetalh w9, w10, [x11]", |
| 1345 | Inst::Ldsetalh { |
| 1346 | rs: W9, |
| 1347 | rt: W10, |
| 1348 | rn: X11, |
| 1349 | }, |
| 1350 | ); |
| 1351 | } |
| 1352 | #[test] |
| 1353 | fn sys_swpal() { |
| 1354 | verify( |
| 1355 | "swpal w0, w0, [x8]", |
| 1356 | Inst::Swpal32 { |
| 1357 | rs: W0, |
| 1358 | rt: W0, |
| 1359 | rn: X8, |
| 1360 | }, |
| 1361 | ); |
| 1362 | } |
| 1363 | #[test] |
| 1364 | fn sys_swpalb() { |
| 1365 | verify( |
| 1366 | "swpalb w8, w9, [x10]", |
| 1367 | Inst::Swpalb { |
| 1368 | rs: W8, |
| 1369 | rt: W9, |
| 1370 | rn: X10, |
| 1371 | }, |
| 1372 | ); |
| 1373 | } |
| 1374 | #[test] |
| 1375 | fn sys_swpalh() { |
| 1376 | verify( |
| 1377 | "swpalh w11, w12, [x13]", |
| 1378 | Inst::Swpalh { |
| 1379 | rs: W11, |
| 1380 | rt: W12, |
| 1381 | rn: X13, |
| 1382 | }, |
| 1383 | ); |
| 1384 | } |
| 1385 | #[test] |
| 1386 | fn sys_casalb() { |
| 1387 | verify( |
| 1388 | "casalb w6, w7, [x8]", |
| 1389 | Inst::Casalb { |
| 1390 | rs: W6, |
| 1391 | rt: W7, |
| 1392 | rn: X8, |
| 1393 | }, |
| 1394 | ); |
| 1395 | } |
| 1396 | #[test] |
| 1397 | fn sys_casalh() { |
| 1398 | verify( |
| 1399 | "casalh w9, w10, [x11]", |
| 1400 | Inst::Casalh { |
| 1401 | rs: W9, |
| 1402 | rt: W10, |
| 1403 | rn: X11, |
| 1404 | }, |
| 1405 | ); |
| 1406 | } |
| 1407 | #[test] |
| 1408 | fn sys_subs_uxtb() { |
| 1409 | verify( |
| 1410 | "subs w10, w8, w9, uxtb", |
| 1411 | Inst::SubsExtReg { |
| 1412 | rd: W10, |
| 1413 | rn: W8, |
| 1414 | rm: W9, |
| 1415 | extend: RegExtend::Uxtb, |
| 1416 | amount: 0, |
| 1417 | sf: false, |
| 1418 | }, |
| 1419 | ); |
| 1420 | } |
| 1421 | #[test] |
| 1422 | fn sys_subs_uxth() { |
| 1423 | verify( |
| 1424 | "subs w11, w12, w13, uxth", |
| 1425 | Inst::SubsExtReg { |
| 1426 | rd: W11, |
| 1427 | rn: W12, |
| 1428 | rm: W13, |
| 1429 | extend: RegExtend::Uxth, |
| 1430 | amount: 0, |
| 1431 | sf: false, |
| 1432 | }, |
| 1433 | ); |
| 1434 | } |
| 1435 | #[test] |
| 1436 | fn sys_subs_sxtb() { |
| 1437 | verify( |
| 1438 | "subs x14, x15, w16, sxtb", |
| 1439 | Inst::SubsExtReg { |
| 1440 | rd: X14, |
| 1441 | rn: X15, |
| 1442 | rm: W16, |
| 1443 | extend: RegExtend::Sxtb, |
| 1444 | amount: 0, |
| 1445 | sf: true, |
| 1446 | }, |
| 1447 | ); |
| 1448 | } |
| 1449 | #[test] |
| 1450 | fn sys_subs_sxth() { |
| 1451 | verify( |
| 1452 | "subs x17, x18, w19, sxth #1", |
| 1453 | Inst::SubsExtReg { |
| 1454 | rd: X17, |
| 1455 | rn: X18, |
| 1456 | rm: W19, |
| 1457 | extend: RegExtend::Sxth, |
| 1458 | amount: 1, |
| 1459 | sf: true, |
| 1460 | }, |
| 1461 | ); |
| 1462 | } |
| 1463 | #[test] |
| 1464 | fn sys_swpal_x() { |
| 1465 | verify( |
| 1466 | "swpal x1, x2, [x3]", |
| 1467 | Inst::Swpal64 { |
| 1468 | rs: X1, |
| 1469 | rt: X2, |
| 1470 | rn: X3, |
| 1471 | }, |
| 1472 | ); |
| 1473 | } |
| 1474 | #[test] |
| 1475 | fn sys_casal() { |
| 1476 | verify( |
| 1477 | "casal w4, w5, [x6]", |
| 1478 | Inst::Casal32 { |
| 1479 | rs: W4, |
| 1480 | rt: W5, |
| 1481 | rn: X6, |
| 1482 | }, |
| 1483 | ); |
| 1484 | } |
| 1485 | #[test] |
| 1486 | fn sys_casal_x() { |
| 1487 | verify( |
| 1488 | "casal x7, x8, [x9]", |
| 1489 | Inst::Casal64 { |
| 1490 | rs: X7, |
| 1491 | rt: X8, |
| 1492 | rn: X9, |
| 1493 | }, |
| 1494 | ); |
| 1495 | } |
| 1496 | #[test] |
| 1497 | fn sys_ldrsw_lit() { |
| 1498 | verify("ldrsw x1, #8", Inst::LdrswLit { rt: X1, offset: 8 }); |
| 1499 | } |
| 1500 | #[test] |
| 1501 | fn sys_ldr_d() { |
| 1502 | verify( |
| 1503 | "ldr d0, [x1]", |
| 1504 | Inst::LdrFpImm64 { |
| 1505 | rt: D0, |
| 1506 | rn: X1, |
| 1507 | offset: 0, |
| 1508 | }, |
| 1509 | ); |
| 1510 | } |
| 1511 | #[test] |
| 1512 | fn sys_ldr_q() { |
| 1513 | verify( |
| 1514 | "ldr q0, [sp, #16]", |
| 1515 | Inst::LdrFpImm128 { |
| 1516 | rt: FpReg::new(0), |
| 1517 | rn: SP, |
| 1518 | offset: 16, |
| 1519 | }, |
| 1520 | ); |
| 1521 | } |
| 1522 | #[test] |
| 1523 | fn sys_ldr_h() { |
| 1524 | verify( |
| 1525 | "ldr h2, [sp, #14]", |
| 1526 | Inst::LdrFpImm16 { |
| 1527 | rt: FpReg::new(2), |
| 1528 | rn: SP, |
| 1529 | offset: 14, |
| 1530 | }, |
| 1531 | ); |
| 1532 | } |
| 1533 | #[test] |
| 1534 | fn sys_ldr_b() { |
| 1535 | verify( |
| 1536 | "ldr b2, [sp, #15]", |
| 1537 | Inst::LdrFpImm8 { |
| 1538 | rt: FpReg::new(2), |
| 1539 | rn: SP, |
| 1540 | offset: 15, |
| 1541 | }, |
| 1542 | ); |
| 1543 | } |
| 1544 | #[test] |
| 1545 | fn sys_str_q() { |
| 1546 | verify( |
| 1547 | "str q1, [x0]", |
| 1548 | Inst::StrFpImm128 { |
| 1549 | rt: FpReg::new(1), |
| 1550 | rn: X0, |
| 1551 | offset: 0, |
| 1552 | }, |
| 1553 | ); |
| 1554 | } |
| 1555 | #[test] |
| 1556 | fn sys_str_h() { |
| 1557 | verify( |
| 1558 | "str h2, [sp, #14]", |
| 1559 | Inst::StrFpImm16 { |
| 1560 | rt: FpReg::new(2), |
| 1561 | rn: SP, |
| 1562 | offset: 14, |
| 1563 | }, |
| 1564 | ); |
| 1565 | } |
| 1566 | #[test] |
| 1567 | fn sys_str_b() { |
| 1568 | verify( |
| 1569 | "str b2, [sp, #15]", |
| 1570 | Inst::StrFpImm8 { |
| 1571 | rt: FpReg::new(2), |
| 1572 | rn: SP, |
| 1573 | offset: 15, |
| 1574 | }, |
| 1575 | ); |
| 1576 | } |
| 1577 | #[test] |
| 1578 | fn sys_ldr_q_lit() { |
| 1579 | verify( |
| 1580 | "ldr q0, #16", |
| 1581 | Inst::LdrFpLit128 { |
| 1582 | rt: FpReg::new(0), |
| 1583 | offset: 16, |
| 1584 | }, |
| 1585 | ); |
| 1586 | } |
| 1587 | #[test] |
| 1588 | fn sys_ldr_q_reg() { |
| 1589 | verify( |
| 1590 | "ldr q0, [x1, x2]", |
| 1591 | Inst::LdrFpReg128 { |
| 1592 | rt: FpReg::new(0), |
| 1593 | rn: X1, |
| 1594 | rm: X2, |
| 1595 | extend: AddrExtend::Lsl, |
| 1596 | shift: false, |
| 1597 | }, |
| 1598 | ); |
| 1599 | } |
| 1600 | #[test] |
| 1601 | fn sys_str_q_reg_uxtw() { |
| 1602 | verify( |
| 1603 | "str q1, [x3, w4, uxtw #4]", |
| 1604 | Inst::StrFpReg128 { |
| 1605 | rt: FpReg::new(1), |
| 1606 | rn: X3, |
| 1607 | rm: W4, |
| 1608 | extend: AddrExtend::Uxtw, |
| 1609 | shift: true, |
| 1610 | }, |
| 1611 | ); |
| 1612 | } |
| 1613 | #[test] |
| 1614 | fn sys_ldr_q_post() { |
| 1615 | verify( |
| 1616 | "ldr q0, [sp], #16", |
| 1617 | Inst::LdrFpPost128 { |
| 1618 | rt: FpReg::new(0), |
| 1619 | rn: SP, |
| 1620 | offset: 16, |
| 1621 | }, |
| 1622 | ); |
| 1623 | } |
| 1624 | #[test] |
| 1625 | fn sys_str_q_pre() { |
| 1626 | verify( |
| 1627 | "str q1, [sp, #-16]!", |
| 1628 | Inst::StrFpPre128 { |
| 1629 | rt: FpReg::new(1), |
| 1630 | rn: SP, |
| 1631 | offset: -16, |
| 1632 | }, |
| 1633 | ); |
| 1634 | } |
| 1635 | #[test] |
| 1636 | fn sys_str_d_off() { |
| 1637 | verify( |
| 1638 | "str d2, [x3, #16]", |
| 1639 | Inst::StrFpImm64 { |
| 1640 | rt: D2, |
| 1641 | rn: X3, |
| 1642 | offset: 16, |
| 1643 | }, |
| 1644 | ); |
| 1645 | } |
| 1646 | #[test] |
| 1647 | fn sys_ldr_s_reg() { |
| 1648 | verify( |
| 1649 | "ldr s4, [x5, x6]", |
| 1650 | Inst::LdrFpReg32 { |
| 1651 | rt: S4, |
| 1652 | rn: X5, |
| 1653 | rm: X6, |
| 1654 | extend: AddrExtend::Lsl, |
| 1655 | shift: false, |
| 1656 | }, |
| 1657 | ); |
| 1658 | } |
| 1659 | #[test] |
| 1660 | fn sys_str_s_reg_uxtw() { |
| 1661 | verify( |
| 1662 | "str s7, [x8, w9, uxtw #2]", |
| 1663 | Inst::StrFpReg32 { |
| 1664 | rt: S7, |
| 1665 | rn: X8, |
| 1666 | rm: W9, |
| 1667 | extend: AddrExtend::Uxtw, |
| 1668 | shift: true, |
| 1669 | }, |
| 1670 | ); |
| 1671 | } |
| 1672 | #[test] |
| 1673 | fn sys_ldr_d_lit() { |
| 1674 | verify("ldr d10, #8", Inst::LdrFpLit64 { rt: D10, offset: 8 }); |
| 1675 | } |
| 1676 | #[test] |
| 1677 | fn sys_ldr_d_post() { |
| 1678 | verify( |
| 1679 | "ldr d0, [sp], #8", |
| 1680 | Inst::LdrFpPost64 { |
| 1681 | rt: D0, |
| 1682 | rn: SP, |
| 1683 | offset: 8, |
| 1684 | }, |
| 1685 | ); |
| 1686 | } |
| 1687 | #[test] |
| 1688 | fn sys_str_s_pre() { |
| 1689 | verify( |
| 1690 | "str s3, [sp, #-8]!", |
| 1691 | Inst::StrFpPre32 { |
| 1692 | rt: S3, |
| 1693 | rn: SP, |
| 1694 | offset: -8, |
| 1695 | }, |
| 1696 | ); |
| 1697 | } |
| 1698 | |
| 1699 | #[test] |
| 1700 | fn sys_str_s_neg_offset() { |
| 1701 | verify( |
| 1702 | "str s8, [x29, #-4]", |
| 1703 | Inst::SturFp32 { |
| 1704 | rt: S8, |
| 1705 | rn: X29, |
| 1706 | offset: -4, |
| 1707 | }, |
| 1708 | ); |
| 1709 | } |
| 1710 | |
| 1711 | #[test] |
| 1712 | fn sys_ldr_s_neg_offset() { |
| 1713 | verify( |
| 1714 | "ldr s9, [x29, #-4]", |
| 1715 | Inst::LdurFp32 { |
| 1716 | rt: S9, |
| 1717 | rn: X29, |
| 1718 | offset: -4, |
| 1719 | }, |
| 1720 | ); |
| 1721 | } |
| 1722 | |
| 1723 | // ---- Address generation ---- |
| 1724 | |
| 1725 | #[test] |
| 1726 | fn sys_adr() { |
| 1727 | verify("adr x0, #8", Inst::Adr { rd: X0, imm: 8 }); |
| 1728 | } |
| 1729 | #[test] |
| 1730 | fn sys_adrp_tlvp() { |
| 1731 | verify( |
| 1732 | "adrp x0, _tls_counter@TLVPPAGE", |
| 1733 | Inst::Adrp { rd: X0, imm: 0 }, |
| 1734 | ); |
| 1735 | } |
| 1736 | |
| 1737 | // ---- Load/Store pair ---- |
| 1738 | |
| 1739 | #[test] |
| 1740 | fn sys_stp_pre() { |
| 1741 | verify( |
| 1742 | "stp x29, x30, [sp, #-32]!", |
| 1743 | Inst::StpPre64 { |
| 1744 | rt1: X29, |
| 1745 | rt2: X30, |
| 1746 | rn: SP, |
| 1747 | offset: -32, |
| 1748 | }, |
| 1749 | ); |
| 1750 | } |
| 1751 | #[test] |
| 1752 | fn sys_ldp_post() { |
| 1753 | verify( |
| 1754 | "ldp x29, x30, [sp], #32", |
| 1755 | Inst::LdpPost64 { |
| 1756 | rt1: X29, |
| 1757 | rt2: X30, |
| 1758 | rn: SP, |
| 1759 | offset: 32, |
| 1760 | }, |
| 1761 | ); |
| 1762 | } |
| 1763 | #[test] |
| 1764 | fn sys_stp_off() { |
| 1765 | verify( |
| 1766 | "stp x19, x20, [sp, #32]", |
| 1767 | Inst::StpOff64 { |
| 1768 | rt1: X19, |
| 1769 | rt2: X20, |
| 1770 | rn: SP, |
| 1771 | offset: 32, |
| 1772 | }, |
| 1773 | ); |
| 1774 | } |
| 1775 | #[test] |
| 1776 | fn sys_ldp_off() { |
| 1777 | verify( |
| 1778 | "ldp x21, x22, [sp, #48]", |
| 1779 | Inst::LdpOff64 { |
| 1780 | rt1: X21, |
| 1781 | rt2: X22, |
| 1782 | rn: SP, |
| 1783 | offset: 48, |
| 1784 | }, |
| 1785 | ); |
| 1786 | } |
| 1787 | #[test] |
| 1788 | fn sys_ldp_off32() { |
| 1789 | verify( |
| 1790 | "ldp w9, w8, [x8]", |
| 1791 | Inst::LdpOff32 { |
| 1792 | rt1: W9, |
| 1793 | rt2: W8, |
| 1794 | rn: X8, |
| 1795 | offset: 0, |
| 1796 | }, |
| 1797 | ); |
| 1798 | } |
| 1799 | #[test] |
| 1800 | fn sys_stp_off32() { |
| 1801 | verify( |
| 1802 | "stp w1, w2, [sp, #16]", |
| 1803 | Inst::StpOff32 { |
| 1804 | rt1: W1, |
| 1805 | rt2: W2, |
| 1806 | rn: SP, |
| 1807 | offset: 16, |
| 1808 | }, |
| 1809 | ); |
| 1810 | } |
| 1811 | #[test] |
| 1812 | fn sys_ldp_post32() { |
| 1813 | verify( |
| 1814 | "ldp w9, w8, [sp], #8", |
| 1815 | Inst::LdpPost32 { |
| 1816 | rt1: W9, |
| 1817 | rt2: W8, |
| 1818 | rn: SP, |
| 1819 | offset: 8, |
| 1820 | }, |
| 1821 | ); |
| 1822 | } |
| 1823 | #[test] |
| 1824 | fn sys_ldp_pre32() { |
| 1825 | verify( |
| 1826 | "ldp w9, w8, [sp, #-8]!", |
| 1827 | Inst::LdpPre32 { |
| 1828 | rt1: W9, |
| 1829 | rt2: W8, |
| 1830 | rn: SP, |
| 1831 | offset: -8, |
| 1832 | }, |
| 1833 | ); |
| 1834 | } |
| 1835 | #[test] |
| 1836 | fn sys_ldp_d_pre() { |
| 1837 | verify( |
| 1838 | "ldp d8, d9, [sp, #-16]!", |
| 1839 | Inst::LdpFpPre64 { |
| 1840 | rt1: D8, |
| 1841 | rt2: D9, |
| 1842 | rn: SP, |
| 1843 | offset: -16, |
| 1844 | }, |
| 1845 | ); |
| 1846 | } |
| 1847 | #[test] |
| 1848 | fn sys_stp_d_post() { |
| 1849 | verify( |
| 1850 | "stp d10, d11, [sp], #16", |
| 1851 | Inst::StpFpPost64 { |
| 1852 | rt1: D10, |
| 1853 | rt2: D11, |
| 1854 | rn: SP, |
| 1855 | offset: 16, |
| 1856 | }, |
| 1857 | ); |
| 1858 | } |
| 1859 | #[test] |
| 1860 | fn sys_ldp_d_off() { |
| 1861 | verify( |
| 1862 | "ldp d12, d13, [sp, #32]", |
| 1863 | Inst::LdpFpOff64 { |
| 1864 | rt1: D12, |
| 1865 | rt2: D13, |
| 1866 | rn: SP, |
| 1867 | offset: 32, |
| 1868 | }, |
| 1869 | ); |
| 1870 | } |
| 1871 | #[test] |
| 1872 | fn sys_stp_s_post() { |
| 1873 | verify( |
| 1874 | "stp s0, s1, [sp], #8", |
| 1875 | Inst::StpFpPost32 { |
| 1876 | rt1: S0, |
| 1877 | rt2: S1, |
| 1878 | rn: SP, |
| 1879 | offset: 8, |
| 1880 | }, |
| 1881 | ); |
| 1882 | } |
| 1883 | #[test] |
| 1884 | fn sys_ldp_s_pre() { |
| 1885 | verify( |
| 1886 | "ldp s2, s3, [sp, #-8]!", |
| 1887 | Inst::LdpFpPre32 { |
| 1888 | rt1: S2, |
| 1889 | rt2: S3, |
| 1890 | rn: SP, |
| 1891 | offset: -8, |
| 1892 | }, |
| 1893 | ); |
| 1894 | } |
| 1895 | #[test] |
| 1896 | fn sys_stp_q_pre() { |
| 1897 | verify( |
| 1898 | "stp q0, q1, [sp, #-32]!", |
| 1899 | Inst::StpFpPre128 { |
| 1900 | rt1: FpReg::new(0), |
| 1901 | rt2: FpReg::new(1), |
| 1902 | rn: SP, |
| 1903 | offset: -32, |
| 1904 | }, |
| 1905 | ); |
| 1906 | } |
| 1907 | #[test] |
| 1908 | fn sys_ldp_q_post() { |
| 1909 | verify( |
| 1910 | "ldp q2, q3, [sp], #32", |
| 1911 | Inst::LdpFpPost128 { |
| 1912 | rt1: FpReg::new(2), |
| 1913 | rt2: FpReg::new(3), |
| 1914 | rn: SP, |
| 1915 | offset: 32, |
| 1916 | }, |
| 1917 | ); |
| 1918 | } |
| 1919 | #[test] |
| 1920 | fn sys_ldp_q_off() { |
| 1921 | verify( |
| 1922 | "ldp q4, q5, [sp, #64]", |
| 1923 | Inst::LdpFpOff128 { |
| 1924 | rt1: FpReg::new(4), |
| 1925 | rt2: FpReg::new(5), |
| 1926 | rn: SP, |
| 1927 | offset: 64, |
| 1928 | }, |
| 1929 | ); |
| 1930 | } |
| 1931 | #[test] |
| 1932 | fn sys_ldp_s_off() { |
| 1933 | verify( |
| 1934 | "ldp s4, s5, [sp, #16]", |
| 1935 | Inst::LdpFpOff32 { |
| 1936 | rt1: S4, |
| 1937 | rt2: S5, |
| 1938 | rn: SP, |
| 1939 | offset: 16, |
| 1940 | }, |
| 1941 | ); |
| 1942 | } |
| 1943 | |
| 1944 | // ---- FP arithmetic ---- |
| 1945 | |
| 1946 | #[test] |
| 1947 | fn sys_fadd_d() { |
| 1948 | verify( |
| 1949 | "fadd d5, d6, d7", |
| 1950 | Inst::FaddD { |
| 1951 | rd: D5, |
| 1952 | rn: D6, |
| 1953 | rm: D7, |
| 1954 | }, |
| 1955 | ); |
| 1956 | } |
| 1957 | #[test] |
| 1958 | fn sys_fsub_d() { |
| 1959 | verify( |
| 1960 | "fsub d5, d6, d7", |
| 1961 | Inst::FsubD { |
| 1962 | rd: D5, |
| 1963 | rn: D6, |
| 1964 | rm: D7, |
| 1965 | }, |
| 1966 | ); |
| 1967 | } |
| 1968 | #[test] |
| 1969 | fn sys_fmul_d() { |
| 1970 | verify( |
| 1971 | "fmul d5, d6, d7", |
| 1972 | Inst::FmulD { |
| 1973 | rd: D5, |
| 1974 | rn: D6, |
| 1975 | rm: D7, |
| 1976 | }, |
| 1977 | ); |
| 1978 | } |
| 1979 | #[test] |
| 1980 | fn sys_fdiv_d() { |
| 1981 | verify( |
| 1982 | "fdiv d5, d6, d7", |
| 1983 | Inst::FdivD { |
| 1984 | rd: D5, |
| 1985 | rn: D6, |
| 1986 | rm: D7, |
| 1987 | }, |
| 1988 | ); |
| 1989 | } |
| 1990 | #[test] |
| 1991 | fn sys_fadd_s() { |
| 1992 | verify( |
| 1993 | "fadd s5, s6, s7", |
| 1994 | Inst::FaddS { |
| 1995 | rd: S5, |
| 1996 | rn: S6, |
| 1997 | rm: S7, |
| 1998 | }, |
| 1999 | ); |
| 2000 | } |
| 2001 | #[test] |
| 2002 | fn sys_fadd_2d() { |
| 2003 | verify( |
| 2004 | "fadd.2d v0, v1, v2", |
| 2005 | Inst::FaddV2D { |
| 2006 | rd: FpReg::new(0), |
| 2007 | rn: FpReg::new(1), |
| 2008 | rm: FpReg::new(2), |
| 2009 | }, |
| 2010 | ); |
| 2011 | } |
| 2012 | #[test] |
| 2013 | fn sys_fadd_4s() { |
| 2014 | verify( |
| 2015 | "fadd.4s v0, v1, v2", |
| 2016 | Inst::FaddV4S { |
| 2017 | rd: FpReg::new(0), |
| 2018 | rn: FpReg::new(1), |
| 2019 | rm: FpReg::new(2), |
| 2020 | }, |
| 2021 | ); |
| 2022 | } |
| 2023 | #[test] |
| 2024 | fn sys_add_4s() { |
| 2025 | verify( |
| 2026 | "add.4s v0, v1, v2", |
| 2027 | Inst::AddV4S { |
| 2028 | rd: FpReg::new(0), |
| 2029 | rn: FpReg::new(1), |
| 2030 | rm: FpReg::new(2), |
| 2031 | }, |
| 2032 | ); |
| 2033 | } |
| 2034 | #[test] |
| 2035 | fn sys_addp_2d() { |
| 2036 | verify( |
| 2037 | "addp.2d v0, v1, v2", |
| 2038 | Inst::AddpV2D { |
| 2039 | rd: FpReg::new(0), |
| 2040 | rn: FpReg::new(1), |
| 2041 | rm: FpReg::new(2), |
| 2042 | }, |
| 2043 | ); |
| 2044 | } |
| 2045 | #[test] |
| 2046 | fn sys_addp_16b() { |
| 2047 | verify( |
| 2048 | "addp.16b v6, v7, v8", |
| 2049 | Inst::AddpV16B { |
| 2050 | rd: FpReg::new(6), |
| 2051 | rn: FpReg::new(7), |
| 2052 | rm: FpReg::new(8), |
| 2053 | }, |
| 2054 | ); |
| 2055 | } |
| 2056 | #[test] |
| 2057 | fn sys_addp_8h() { |
| 2058 | verify( |
| 2059 | "addp.8h v0, v1, v2", |
| 2060 | Inst::AddpV8H { |
| 2061 | rd: FpReg::new(0), |
| 2062 | rn: FpReg::new(1), |
| 2063 | rm: FpReg::new(2), |
| 2064 | }, |
| 2065 | ); |
| 2066 | } |
| 2067 | #[test] |
| 2068 | fn sys_addp_4s() { |
| 2069 | verify( |
| 2070 | "addp.4s v0, v1, v2", |
| 2071 | Inst::AddpV4S { |
| 2072 | rd: FpReg::new(0), |
| 2073 | rn: FpReg::new(1), |
| 2074 | rm: FpReg::new(2), |
| 2075 | }, |
| 2076 | ); |
| 2077 | } |
| 2078 | #[test] |
| 2079 | fn sys_fmax_2d() { |
| 2080 | verify( |
| 2081 | "fmax.2d v0, v0, v1", |
| 2082 | Inst::FmaxV2D { |
| 2083 | rd: FpReg::new(0), |
| 2084 | rn: FpReg::new(0), |
| 2085 | rm: FpReg::new(1), |
| 2086 | }, |
| 2087 | ); |
| 2088 | } |
| 2089 | #[test] |
| 2090 | fn sys_fmax_4s() { |
| 2091 | verify( |
| 2092 | "fmax.4s v0, v0, v1", |
| 2093 | Inst::FmaxV4S { |
| 2094 | rd: FpReg::new(0), |
| 2095 | rn: FpReg::new(0), |
| 2096 | rm: FpReg::new(1), |
| 2097 | }, |
| 2098 | ); |
| 2099 | } |
| 2100 | #[test] |
| 2101 | fn sys_fmaxnm_4s() { |
| 2102 | verify( |
| 2103 | "fmaxnm.4s v0, v1, v2", |
| 2104 | Inst::FmaxnmV4S { |
| 2105 | rd: FpReg::new(0), |
| 2106 | rn: FpReg::new(1), |
| 2107 | rm: FpReg::new(2), |
| 2108 | }, |
| 2109 | ); |
| 2110 | } |
| 2111 | #[test] |
| 2112 | fn sys_fmaxnm_2d() { |
| 2113 | verify( |
| 2114 | "fmaxnm.2d v0, v0, v1", |
| 2115 | Inst::FmaxnmV2D { |
| 2116 | rd: FpReg::new(0), |
| 2117 | rn: FpReg::new(0), |
| 2118 | rm: FpReg::new(1), |
| 2119 | }, |
| 2120 | ); |
| 2121 | } |
| 2122 | #[test] |
| 2123 | fn sys_fmin_2d() { |
| 2124 | verify( |
| 2125 | "fmin.2d v2, v3, v4", |
| 2126 | Inst::FminV2D { |
| 2127 | rd: FpReg::new(2), |
| 2128 | rn: FpReg::new(3), |
| 2129 | rm: FpReg::new(4), |
| 2130 | }, |
| 2131 | ); |
| 2132 | } |
| 2133 | #[test] |
| 2134 | fn sys_fmin_4s() { |
| 2135 | verify( |
| 2136 | "fmin.4s v2, v3, v4", |
| 2137 | Inst::FminV4S { |
| 2138 | rd: FpReg::new(2), |
| 2139 | rn: FpReg::new(3), |
| 2140 | rm: FpReg::new(4), |
| 2141 | }, |
| 2142 | ); |
| 2143 | } |
| 2144 | #[test] |
| 2145 | fn sys_fminnm_4s() { |
| 2146 | verify( |
| 2147 | "fminnm.4s v3, v4, v5", |
| 2148 | Inst::FminnmV4S { |
| 2149 | rd: FpReg::new(3), |
| 2150 | rn: FpReg::new(4), |
| 2151 | rm: FpReg::new(5), |
| 2152 | }, |
| 2153 | ); |
| 2154 | } |
| 2155 | #[test] |
| 2156 | fn sys_fminnm_2d() { |
| 2157 | verify( |
| 2158 | "fminnm.2d v2, v3, v4", |
| 2159 | Inst::FminnmV2D { |
| 2160 | rd: FpReg::new(2), |
| 2161 | rn: FpReg::new(3), |
| 2162 | rm: FpReg::new(4), |
| 2163 | }, |
| 2164 | ); |
| 2165 | } |
| 2166 | #[test] |
| 2167 | fn sys_smax_4s() { |
| 2168 | verify( |
| 2169 | "smax.4s v5, v6, v7", |
| 2170 | Inst::SmaxV4S { |
| 2171 | rd: FpReg::new(5), |
| 2172 | rn: FpReg::new(6), |
| 2173 | rm: FpReg::new(7), |
| 2174 | }, |
| 2175 | ); |
| 2176 | } |
| 2177 | #[test] |
| 2178 | fn sys_smaxp_4s() { |
| 2179 | verify( |
| 2180 | "smaxp.4s v6, v7, v8", |
| 2181 | Inst::SmaxpV4S { |
| 2182 | rd: FpReg::new(6), |
| 2183 | rn: FpReg::new(7), |
| 2184 | rm: FpReg::new(8), |
| 2185 | }, |
| 2186 | ); |
| 2187 | } |
| 2188 | #[test] |
| 2189 | fn sys_smaxp_16b() { |
| 2190 | verify( |
| 2191 | "smaxp.16b v6, v7, v8", |
| 2192 | Inst::SmaxpV16B { |
| 2193 | rd: FpReg::new(6), |
| 2194 | rn: FpReg::new(7), |
| 2195 | rm: FpReg::new(8), |
| 2196 | }, |
| 2197 | ); |
| 2198 | } |
| 2199 | #[test] |
| 2200 | fn sys_smaxp_8h() { |
| 2201 | verify( |
| 2202 | "smaxp.8h v6, v7, v8", |
| 2203 | Inst::SmaxpV8H { |
| 2204 | rd: FpReg::new(6), |
| 2205 | rn: FpReg::new(7), |
| 2206 | rm: FpReg::new(8), |
| 2207 | }, |
| 2208 | ); |
| 2209 | } |
| 2210 | #[test] |
| 2211 | fn sys_smin_4s() { |
| 2212 | verify( |
| 2213 | "smin.4s v8, v9, v10", |
| 2214 | Inst::SminV4S { |
| 2215 | rd: FpReg::new(8), |
| 2216 | rn: FpReg::new(9), |
| 2217 | rm: FpReg::new(10), |
| 2218 | }, |
| 2219 | ); |
| 2220 | } |
| 2221 | #[test] |
| 2222 | fn sys_sminp_16b() { |
| 2223 | verify( |
| 2224 | "sminp.16b v9, v10, v11", |
| 2225 | Inst::SminpV16B { |
| 2226 | rd: FpReg::new(9), |
| 2227 | rn: FpReg::new(10), |
| 2228 | rm: FpReg::new(11), |
| 2229 | }, |
| 2230 | ); |
| 2231 | } |
| 2232 | #[test] |
| 2233 | fn sys_sminp_4s() { |
| 2234 | verify( |
| 2235 | "sminp.4s v9, v10, v11", |
| 2236 | Inst::SminpV4S { |
| 2237 | rd: FpReg::new(9), |
| 2238 | rn: FpReg::new(10), |
| 2239 | rm: FpReg::new(11), |
| 2240 | }, |
| 2241 | ); |
| 2242 | } |
| 2243 | #[test] |
| 2244 | fn sys_sminp_8h() { |
| 2245 | verify( |
| 2246 | "sminp.8h v9, v10, v11", |
| 2247 | Inst::SminpV8H { |
| 2248 | rd: FpReg::new(9), |
| 2249 | rn: FpReg::new(10), |
| 2250 | rm: FpReg::new(11), |
| 2251 | }, |
| 2252 | ); |
| 2253 | } |
| 2254 | #[test] |
| 2255 | fn sys_umax_4s() { |
| 2256 | verify( |
| 2257 | "umax.4s v0, v0, v1", |
| 2258 | Inst::UmaxV4S { |
| 2259 | rd: FpReg::new(0), |
| 2260 | rn: FpReg::new(0), |
| 2261 | rm: FpReg::new(1), |
| 2262 | }, |
| 2263 | ); |
| 2264 | } |
| 2265 | #[test] |
| 2266 | fn sys_umaxp_16b() { |
| 2267 | verify( |
| 2268 | "umaxp.16b v0, v1, v2", |
| 2269 | Inst::UmaxpV16B { |
| 2270 | rd: FpReg::new(0), |
| 2271 | rn: FpReg::new(1), |
| 2272 | rm: FpReg::new(2), |
| 2273 | }, |
| 2274 | ); |
| 2275 | } |
| 2276 | #[test] |
| 2277 | fn sys_umaxp_8h() { |
| 2278 | verify( |
| 2279 | "umaxp.8h v0, v1, v2", |
| 2280 | Inst::UmaxpV8H { |
| 2281 | rd: FpReg::new(0), |
| 2282 | rn: FpReg::new(1), |
| 2283 | rm: FpReg::new(2), |
| 2284 | }, |
| 2285 | ); |
| 2286 | } |
| 2287 | #[test] |
| 2288 | fn sys_umaxp_4s() { |
| 2289 | verify( |
| 2290 | "umaxp.4s v0, v1, v2", |
| 2291 | Inst::UmaxpV4S { |
| 2292 | rd: FpReg::new(0), |
| 2293 | rn: FpReg::new(1), |
| 2294 | rm: FpReg::new(2), |
| 2295 | }, |
| 2296 | ); |
| 2297 | } |
| 2298 | #[test] |
| 2299 | fn sys_uminp_16b() { |
| 2300 | verify( |
| 2301 | "uminp.16b v3, v4, v5", |
| 2302 | Inst::UminpV16B { |
| 2303 | rd: FpReg::new(3), |
| 2304 | rn: FpReg::new(4), |
| 2305 | rm: FpReg::new(5), |
| 2306 | }, |
| 2307 | ); |
| 2308 | } |
| 2309 | #[test] |
| 2310 | fn sys_uminp_8h() { |
| 2311 | verify( |
| 2312 | "uminp.8h v3, v4, v5", |
| 2313 | Inst::UminpV8H { |
| 2314 | rd: FpReg::new(3), |
| 2315 | rn: FpReg::new(4), |
| 2316 | rm: FpReg::new(5), |
| 2317 | }, |
| 2318 | ); |
| 2319 | } |
| 2320 | #[test] |
| 2321 | fn sys_umin_4s() { |
| 2322 | verify( |
| 2323 | "umin.4s v2, v3, v4", |
| 2324 | Inst::UminV4S { |
| 2325 | rd: FpReg::new(2), |
| 2326 | rn: FpReg::new(3), |
| 2327 | rm: FpReg::new(4), |
| 2328 | }, |
| 2329 | ); |
| 2330 | } |
| 2331 | #[test] |
| 2332 | fn sys_uminp_4s() { |
| 2333 | verify( |
| 2334 | "uminp.4s v3, v4, v5", |
| 2335 | Inst::UminpV4S { |
| 2336 | rd: FpReg::new(3), |
| 2337 | rn: FpReg::new(4), |
| 2338 | rm: FpReg::new(5), |
| 2339 | }, |
| 2340 | ); |
| 2341 | } |
| 2342 | #[test] |
| 2343 | fn sys_addv_4s() { |
| 2344 | verify( |
| 2345 | "addv.4s s0, v0", |
| 2346 | Inst::AddvV4S { |
| 2347 | rd: FpReg::new(0), |
| 2348 | rn: FpReg::new(0), |
| 2349 | }, |
| 2350 | ); |
| 2351 | } |
| 2352 | #[test] |
| 2353 | fn sys_addv_16b() { |
| 2354 | verify( |
| 2355 | "addv.16b b0, v0", |
| 2356 | Inst::AddvV16B { |
| 2357 | rd: FpReg::new(0), |
| 2358 | rn: FpReg::new(0), |
| 2359 | }, |
| 2360 | ); |
| 2361 | } |
| 2362 | #[test] |
| 2363 | fn sys_addv_8h() { |
| 2364 | verify( |
| 2365 | "addv.8h h0, v0", |
| 2366 | Inst::AddvV8H { |
| 2367 | rd: FpReg::new(0), |
| 2368 | rn: FpReg::new(0), |
| 2369 | }, |
| 2370 | ); |
| 2371 | } |
| 2372 | #[test] |
| 2373 | fn sys_faddp_2d() { |
| 2374 | verify( |
| 2375 | "faddp.2d v0, v1, v2", |
| 2376 | Inst::FaddpV2D { |
| 2377 | rd: FpReg::new(0), |
| 2378 | rn: FpReg::new(1), |
| 2379 | rm: FpReg::new(2), |
| 2380 | }, |
| 2381 | ); |
| 2382 | } |
| 2383 | #[test] |
| 2384 | fn sys_faddp_4s() { |
| 2385 | verify( |
| 2386 | "faddp.4s v0, v1, v2", |
| 2387 | Inst::FaddpV4S { |
| 2388 | rd: FpReg::new(0), |
| 2389 | rn: FpReg::new(1), |
| 2390 | rm: FpReg::new(2), |
| 2391 | }, |
| 2392 | ); |
| 2393 | } |
| 2394 | #[test] |
| 2395 | fn sys_fmaxp_2d() { |
| 2396 | verify( |
| 2397 | "fmaxp.2d v3, v4, v5", |
| 2398 | Inst::FmaxpV2D { |
| 2399 | rd: FpReg::new(3), |
| 2400 | rn: FpReg::new(4), |
| 2401 | rm: FpReg::new(5), |
| 2402 | }, |
| 2403 | ); |
| 2404 | } |
| 2405 | #[test] |
| 2406 | fn sys_fmaxp_4s() { |
| 2407 | verify( |
| 2408 | "fmaxp.4s v0, v1, v2", |
| 2409 | Inst::FmaxpV4S { |
| 2410 | rd: FpReg::new(0), |
| 2411 | rn: FpReg::new(1), |
| 2412 | rm: FpReg::new(2), |
| 2413 | }, |
| 2414 | ); |
| 2415 | } |
| 2416 | #[test] |
| 2417 | fn sys_fminp_2d() { |
| 2418 | verify( |
| 2419 | "fminp.2d v6, v7, v8", |
| 2420 | Inst::FminpV2D { |
| 2421 | rd: FpReg::new(6), |
| 2422 | rn: FpReg::new(7), |
| 2423 | rm: FpReg::new(8), |
| 2424 | }, |
| 2425 | ); |
| 2426 | } |
| 2427 | #[test] |
| 2428 | fn sys_fminp_4s() { |
| 2429 | verify( |
| 2430 | "fminp.4s v3, v4, v5", |
| 2431 | Inst::FminpV4S { |
| 2432 | rd: FpReg::new(3), |
| 2433 | rn: FpReg::new(4), |
| 2434 | rm: FpReg::new(5), |
| 2435 | }, |
| 2436 | ); |
| 2437 | } |
| 2438 | #[test] |
| 2439 | fn sys_fmaxnmp_2d() { |
| 2440 | verify( |
| 2441 | "fmaxnmp.2d v0, v1, v2", |
| 2442 | Inst::FmaxnmpV2D { |
| 2443 | rd: FpReg::new(0), |
| 2444 | rn: FpReg::new(1), |
| 2445 | rm: FpReg::new(2), |
| 2446 | }, |
| 2447 | ); |
| 2448 | } |
| 2449 | #[test] |
| 2450 | fn sys_fmaxnmp_4s() { |
| 2451 | verify( |
| 2452 | "fmaxnmp.4s v0, v1, v2", |
| 2453 | Inst::FmaxnmpV4S { |
| 2454 | rd: FpReg::new(0), |
| 2455 | rn: FpReg::new(1), |
| 2456 | rm: FpReg::new(2), |
| 2457 | }, |
| 2458 | ); |
| 2459 | } |
| 2460 | #[test] |
| 2461 | fn sys_fminnmp_2d() { |
| 2462 | verify( |
| 2463 | "fminnmp.2d v3, v4, v5", |
| 2464 | Inst::FminnmpV2D { |
| 2465 | rd: FpReg::new(3), |
| 2466 | rn: FpReg::new(4), |
| 2467 | rm: FpReg::new(5), |
| 2468 | }, |
| 2469 | ); |
| 2470 | } |
| 2471 | #[test] |
| 2472 | fn sys_fminnmp_4s() { |
| 2473 | verify( |
| 2474 | "fminnmp.4s v3, v4, v5", |
| 2475 | Inst::FminnmpV4S { |
| 2476 | rd: FpReg::new(3), |
| 2477 | rn: FpReg::new(4), |
| 2478 | rm: FpReg::new(5), |
| 2479 | }, |
| 2480 | ); |
| 2481 | } |
| 2482 | #[test] |
| 2483 | fn sys_fmla_4s() { |
| 2484 | verify( |
| 2485 | "fmla.4s v0, v1, v2", |
| 2486 | Inst::FmlaV4S { |
| 2487 | rd: FpReg::new(0), |
| 2488 | rn: FpReg::new(1), |
| 2489 | rm: FpReg::new(2), |
| 2490 | }, |
| 2491 | ); |
| 2492 | } |
| 2493 | #[test] |
| 2494 | fn sys_fmla_2d() { |
| 2495 | verify( |
| 2496 | "fmla.2d v0, v1, v2", |
| 2497 | Inst::FmlaV2D { |
| 2498 | rd: FpReg::new(0), |
| 2499 | rn: FpReg::new(1), |
| 2500 | rm: FpReg::new(2), |
| 2501 | }, |
| 2502 | ); |
| 2503 | } |
| 2504 | #[test] |
| 2505 | fn sys_fmls_4s() { |
| 2506 | verify( |
| 2507 | "fmls.4s v3, v4, v5", |
| 2508 | Inst::FmlsV4S { |
| 2509 | rd: FpReg::new(3), |
| 2510 | rn: FpReg::new(4), |
| 2511 | rm: FpReg::new(5), |
| 2512 | }, |
| 2513 | ); |
| 2514 | } |
| 2515 | #[test] |
| 2516 | fn sys_fmls_2d() { |
| 2517 | verify( |
| 2518 | "fmls.2d v3, v4, v5", |
| 2519 | Inst::FmlsV2D { |
| 2520 | rd: FpReg::new(3), |
| 2521 | rn: FpReg::new(4), |
| 2522 | rm: FpReg::new(5), |
| 2523 | }, |
| 2524 | ); |
| 2525 | } |
| 2526 | #[test] |
| 2527 | fn sys_faddp_2s() { |
| 2528 | verify( |
| 2529 | "faddp.2s s3, v4", |
| 2530 | Inst::FaddpV2S { |
| 2531 | rd: FpReg::new(3), |
| 2532 | rn: FpReg::new(4), |
| 2533 | }, |
| 2534 | ); |
| 2535 | } |
| 2536 | #[test] |
| 2537 | fn sys_faddp_2d_scalar() { |
| 2538 | verify( |
| 2539 | "faddp.2d d0, v0", |
| 2540 | Inst::FaddpV2DScalar { |
| 2541 | rd: FpReg::new(0), |
| 2542 | rn: FpReg::new(0), |
| 2543 | }, |
| 2544 | ); |
| 2545 | } |
| 2546 | #[test] |
| 2547 | fn sys_fmaxp_2d_scalar() { |
| 2548 | verify( |
| 2549 | "fmaxp.2d d1, v2", |
| 2550 | Inst::FmaxpV2DScalar { |
| 2551 | rd: FpReg::new(1), |
| 2552 | rn: FpReg::new(2), |
| 2553 | }, |
| 2554 | ); |
| 2555 | } |
| 2556 | #[test] |
| 2557 | fn sys_fminp_2d_scalar() { |
| 2558 | verify( |
| 2559 | "fminp.2d d3, v4", |
| 2560 | Inst::FminpV2DScalar { |
| 2561 | rd: FpReg::new(3), |
| 2562 | rn: FpReg::new(4), |
| 2563 | }, |
| 2564 | ); |
| 2565 | } |
| 2566 | #[test] |
| 2567 | fn sys_fmaxnmp_2d_scalar() { |
| 2568 | verify( |
| 2569 | "fmaxnmp.2d d0, v0", |
| 2570 | Inst::FmaxnmpV2DScalar { |
| 2571 | rd: FpReg::new(0), |
| 2572 | rn: FpReg::new(0), |
| 2573 | }, |
| 2574 | ); |
| 2575 | } |
| 2576 | #[test] |
| 2577 | fn sys_fminnmp_2d_scalar() { |
| 2578 | verify( |
| 2579 | "fminnmp.2d d1, v2", |
| 2580 | Inst::FminnmpV2DScalar { |
| 2581 | rd: FpReg::new(1), |
| 2582 | rn: FpReg::new(2), |
| 2583 | }, |
| 2584 | ); |
| 2585 | } |
| 2586 | #[test] |
| 2587 | fn sys_fmaxv_4s() { |
| 2588 | verify( |
| 2589 | "fmaxv.4s s1, v2", |
| 2590 | Inst::FmaxvV4S { |
| 2591 | rd: FpReg::new(1), |
| 2592 | rn: FpReg::new(2), |
| 2593 | }, |
| 2594 | ); |
| 2595 | } |
| 2596 | #[test] |
| 2597 | fn sys_fmaxnmv_4s() { |
| 2598 | verify( |
| 2599 | "fmaxnmv.4s s1, v2", |
| 2600 | Inst::FmaxnmvV4S { |
| 2601 | rd: FpReg::new(1), |
| 2602 | rn: FpReg::new(2), |
| 2603 | }, |
| 2604 | ); |
| 2605 | } |
| 2606 | #[test] |
| 2607 | fn sys_fminv_4s() { |
| 2608 | verify( |
| 2609 | "fminv.4s s3, v4", |
| 2610 | Inst::FminvV4S { |
| 2611 | rd: FpReg::new(3), |
| 2612 | rn: FpReg::new(4), |
| 2613 | }, |
| 2614 | ); |
| 2615 | } |
| 2616 | #[test] |
| 2617 | fn sys_fminnmv_4s() { |
| 2618 | verify( |
| 2619 | "fminnmv.4s s3, v4", |
| 2620 | Inst::FminnmvV4S { |
| 2621 | rd: FpReg::new(3), |
| 2622 | rn: FpReg::new(4), |
| 2623 | }, |
| 2624 | ); |
| 2625 | } |
| 2626 | #[test] |
| 2627 | fn sys_umaxv_4s() { |
| 2628 | verify( |
| 2629 | "umaxv.4s s1, v2", |
| 2630 | Inst::UmaxvV4S { |
| 2631 | rd: FpReg::new(1), |
| 2632 | rn: FpReg::new(2), |
| 2633 | }, |
| 2634 | ); |
| 2635 | } |
| 2636 | #[test] |
| 2637 | fn sys_umaxv_16b() { |
| 2638 | verify( |
| 2639 | "umaxv.16b b0, v0", |
| 2640 | Inst::UmaxvV16B { |
| 2641 | rd: FpReg::new(0), |
| 2642 | rn: FpReg::new(0), |
| 2643 | }, |
| 2644 | ); |
| 2645 | } |
| 2646 | #[test] |
| 2647 | fn sys_umaxv_8h() { |
| 2648 | verify( |
| 2649 | "umaxv.8h h0, v0", |
| 2650 | Inst::UmaxvV8H { |
| 2651 | rd: FpReg::new(0), |
| 2652 | rn: FpReg::new(0), |
| 2653 | }, |
| 2654 | ); |
| 2655 | } |
| 2656 | #[test] |
| 2657 | fn sys_smaxv_4s() { |
| 2658 | verify( |
| 2659 | "smaxv.4s s3, v4", |
| 2660 | Inst::SmaxvV4S { |
| 2661 | rd: FpReg::new(3), |
| 2662 | rn: FpReg::new(4), |
| 2663 | }, |
| 2664 | ); |
| 2665 | } |
| 2666 | #[test] |
| 2667 | fn sys_smaxv_16b() { |
| 2668 | verify( |
| 2669 | "smaxv.16b b0, v0", |
| 2670 | Inst::SmaxvV16B { |
| 2671 | rd: FpReg::new(0), |
| 2672 | rn: FpReg::new(0), |
| 2673 | }, |
| 2674 | ); |
| 2675 | } |
| 2676 | #[test] |
| 2677 | fn sys_smaxv_8h() { |
| 2678 | verify( |
| 2679 | "smaxv.8h h0, v0", |
| 2680 | Inst::SmaxvV8H { |
| 2681 | rd: FpReg::new(0), |
| 2682 | rn: FpReg::new(0), |
| 2683 | }, |
| 2684 | ); |
| 2685 | } |
| 2686 | #[test] |
| 2687 | fn sys_uminv_4s() { |
| 2688 | verify( |
| 2689 | "uminv.4s s1, v2", |
| 2690 | Inst::UminvV4S { |
| 2691 | rd: FpReg::new(1), |
| 2692 | rn: FpReg::new(2), |
| 2693 | }, |
| 2694 | ); |
| 2695 | } |
| 2696 | #[test] |
| 2697 | fn sys_uminv_16b() { |
| 2698 | verify( |
| 2699 | "uminv.16b b0, v0", |
| 2700 | Inst::UminvV16B { |
| 2701 | rd: FpReg::new(0), |
| 2702 | rn: FpReg::new(0), |
| 2703 | }, |
| 2704 | ); |
| 2705 | } |
| 2706 | #[test] |
| 2707 | fn sys_uminv_8h() { |
| 2708 | verify( |
| 2709 | "uminv.8h h0, v0", |
| 2710 | Inst::UminvV8H { |
| 2711 | rd: FpReg::new(0), |
| 2712 | rn: FpReg::new(0), |
| 2713 | }, |
| 2714 | ); |
| 2715 | } |
| 2716 | #[test] |
| 2717 | fn sys_sminv_4s() { |
| 2718 | verify( |
| 2719 | "sminv.4s s3, v4", |
| 2720 | Inst::SminvV4S { |
| 2721 | rd: FpReg::new(3), |
| 2722 | rn: FpReg::new(4), |
| 2723 | }, |
| 2724 | ); |
| 2725 | } |
| 2726 | #[test] |
| 2727 | fn sys_sminv_16b() { |
| 2728 | verify( |
| 2729 | "sminv.16b b0, v0", |
| 2730 | Inst::SminvV16B { |
| 2731 | rd: FpReg::new(0), |
| 2732 | rn: FpReg::new(0), |
| 2733 | }, |
| 2734 | ); |
| 2735 | } |
| 2736 | #[test] |
| 2737 | fn sys_sminv_8h() { |
| 2738 | verify( |
| 2739 | "sminv.8h h0, v0", |
| 2740 | Inst::SminvV8H { |
| 2741 | rd: FpReg::new(0), |
| 2742 | rn: FpReg::new(0), |
| 2743 | }, |
| 2744 | ); |
| 2745 | } |
| 2746 | #[test] |
| 2747 | fn sys_fsub_2d() { |
| 2748 | verify( |
| 2749 | "fsub.2d v3, v4, v5", |
| 2750 | Inst::FsubV2D { |
| 2751 | rd: FpReg::new(3), |
| 2752 | rn: FpReg::new(4), |
| 2753 | rm: FpReg::new(5), |
| 2754 | }, |
| 2755 | ); |
| 2756 | } |
| 2757 | #[test] |
| 2758 | fn sys_fsub_4s() { |
| 2759 | verify( |
| 2760 | "fsub.4s v3, v4, v5", |
| 2761 | Inst::FsubV4S { |
| 2762 | rd: FpReg::new(3), |
| 2763 | rn: FpReg::new(4), |
| 2764 | rm: FpReg::new(5), |
| 2765 | }, |
| 2766 | ); |
| 2767 | } |
| 2768 | #[test] |
| 2769 | fn sys_sub_4s() { |
| 2770 | verify( |
| 2771 | "sub.4s v3, v4, v5", |
| 2772 | Inst::SubV4S { |
| 2773 | rd: FpReg::new(3), |
| 2774 | rn: FpReg::new(4), |
| 2775 | rm: FpReg::new(5), |
| 2776 | }, |
| 2777 | ); |
| 2778 | } |
| 2779 | #[test] |
| 2780 | fn sys_fmul_2d() { |
| 2781 | verify( |
| 2782 | "fmul.2d v6, v7, v8", |
| 2783 | Inst::FmulV2D { |
| 2784 | rd: FpReg::new(6), |
| 2785 | rn: FpReg::new(7), |
| 2786 | rm: FpReg::new(8), |
| 2787 | }, |
| 2788 | ); |
| 2789 | } |
| 2790 | #[test] |
| 2791 | fn sys_fmul_4s() { |
| 2792 | verify( |
| 2793 | "fmul.4s v6, v7, v8", |
| 2794 | Inst::FmulV4S { |
| 2795 | rd: FpReg::new(6), |
| 2796 | rn: FpReg::new(7), |
| 2797 | rm: FpReg::new(8), |
| 2798 | }, |
| 2799 | ); |
| 2800 | } |
| 2801 | #[test] |
| 2802 | fn sys_fdiv_2d() { |
| 2803 | verify( |
| 2804 | "fdiv.2d v9, v10, v11", |
| 2805 | Inst::FdivV2D { |
| 2806 | rd: FpReg::new(9), |
| 2807 | rn: FpReg::new(10), |
| 2808 | rm: FpReg::new(11), |
| 2809 | }, |
| 2810 | ); |
| 2811 | } |
| 2812 | #[test] |
| 2813 | fn sys_fabd_2d() { |
| 2814 | verify( |
| 2815 | "fabd.2d v0, v1, v2", |
| 2816 | Inst::FabdV2D { |
| 2817 | rd: FpReg::new(0), |
| 2818 | rn: FpReg::new(1), |
| 2819 | rm: FpReg::new(2), |
| 2820 | }, |
| 2821 | ); |
| 2822 | } |
| 2823 | #[test] |
| 2824 | fn sys_fdiv_4s() { |
| 2825 | verify( |
| 2826 | "fdiv.4s v9, v10, v11", |
| 2827 | Inst::FdivV4S { |
| 2828 | rd: FpReg::new(9), |
| 2829 | rn: FpReg::new(10), |
| 2830 | rm: FpReg::new(11), |
| 2831 | }, |
| 2832 | ); |
| 2833 | } |
| 2834 | #[test] |
| 2835 | fn sys_fabs_4s() { |
| 2836 | verify( |
| 2837 | "fabs.4s v0, v0", |
| 2838 | Inst::FabsV4S { |
| 2839 | rd: FpReg::new(0), |
| 2840 | rn: FpReg::new(0), |
| 2841 | }, |
| 2842 | ); |
| 2843 | } |
| 2844 | #[test] |
| 2845 | fn sys_fneg_4s() { |
| 2846 | verify( |
| 2847 | "fneg.4s v6, v7", |
| 2848 | Inst::FnegV4S { |
| 2849 | rd: FpReg::new(6), |
| 2850 | rn: FpReg::new(7), |
| 2851 | }, |
| 2852 | ); |
| 2853 | } |
| 2854 | #[test] |
| 2855 | fn sys_fsqrt_4s() { |
| 2856 | verify( |
| 2857 | "fsqrt.4s v1, v2", |
| 2858 | Inst::FsqrtV4S { |
| 2859 | rd: FpReg::new(1), |
| 2860 | rn: FpReg::new(2), |
| 2861 | }, |
| 2862 | ); |
| 2863 | } |
| 2864 | #[test] |
| 2865 | fn sys_fabs_2d() { |
| 2866 | verify( |
| 2867 | "fabs.2d v0, v0", |
| 2868 | Inst::FabsV2D { |
| 2869 | rd: FpReg::new(0), |
| 2870 | rn: FpReg::new(0), |
| 2871 | }, |
| 2872 | ); |
| 2873 | } |
| 2874 | #[test] |
| 2875 | fn sys_fneg_2d() { |
| 2876 | verify( |
| 2877 | "fneg.2d v3, v4", |
| 2878 | Inst::FnegV2D { |
| 2879 | rd: FpReg::new(3), |
| 2880 | rn: FpReg::new(4), |
| 2881 | }, |
| 2882 | ); |
| 2883 | } |
| 2884 | #[test] |
| 2885 | fn sys_fsqrt_2d() { |
| 2886 | verify( |
| 2887 | "fsqrt.2d v1, v2", |
| 2888 | Inst::FsqrtV2D { |
| 2889 | rd: FpReg::new(1), |
| 2890 | rn: FpReg::new(2), |
| 2891 | }, |
| 2892 | ); |
| 2893 | } |
| 2894 | #[test] |
| 2895 | fn sys_scvtf_2d() { |
| 2896 | verify( |
| 2897 | "scvtf.2d v0, v0", |
| 2898 | Inst::ScvtfV2D { |
| 2899 | rd: FpReg::new(0), |
| 2900 | rn: FpReg::new(0), |
| 2901 | }, |
| 2902 | ); |
| 2903 | } |
| 2904 | #[test] |
| 2905 | fn sys_ucvtf_2d() { |
| 2906 | verify( |
| 2907 | "ucvtf.2d v1, v2", |
| 2908 | Inst::UcvtfV2D { |
| 2909 | rd: FpReg::new(1), |
| 2910 | rn: FpReg::new(2), |
| 2911 | }, |
| 2912 | ); |
| 2913 | } |
| 2914 | #[test] |
| 2915 | fn sys_fcvtzs_2d() { |
| 2916 | verify( |
| 2917 | "fcvtzs.2d v3, v4", |
| 2918 | Inst::FcvtzsV2D { |
| 2919 | rd: FpReg::new(3), |
| 2920 | rn: FpReg::new(4), |
| 2921 | }, |
| 2922 | ); |
| 2923 | } |
| 2924 | #[test] |
| 2925 | fn sys_fcvtzu_2d() { |
| 2926 | verify( |
| 2927 | "fcvtzu.2d v5, v6", |
| 2928 | Inst::FcvtzuV2D { |
| 2929 | rd: FpReg::new(5), |
| 2930 | rn: FpReg::new(6), |
| 2931 | }, |
| 2932 | ); |
| 2933 | } |
| 2934 | #[test] |
| 2935 | fn sys_frecpe_2d() { |
| 2936 | verify( |
| 2937 | "frecpe.2d v0, v0", |
| 2938 | Inst::FrecpeV2D { |
| 2939 | rd: FpReg::new(0), |
| 2940 | rn: FpReg::new(0), |
| 2941 | }, |
| 2942 | ); |
| 2943 | } |
| 2944 | #[test] |
| 2945 | fn sys_frecps_2d() { |
| 2946 | verify( |
| 2947 | "frecps.2d v1, v2, v3", |
| 2948 | Inst::FrecpsV2D { |
| 2949 | rd: FpReg::new(1), |
| 2950 | rn: FpReg::new(2), |
| 2951 | rm: FpReg::new(3), |
| 2952 | }, |
| 2953 | ); |
| 2954 | } |
| 2955 | #[test] |
| 2956 | fn sys_frsqrte_2d() { |
| 2957 | verify( |
| 2958 | "frsqrte.2d v4, v5", |
| 2959 | Inst::FrsqrteV2D { |
| 2960 | rd: FpReg::new(4), |
| 2961 | rn: FpReg::new(5), |
| 2962 | }, |
| 2963 | ); |
| 2964 | } |
| 2965 | #[test] |
| 2966 | fn sys_frsqrts_2d() { |
| 2967 | verify( |
| 2968 | "frsqrts.2d v6, v7, v8", |
| 2969 | Inst::FrsqrtsV2D { |
| 2970 | rd: FpReg::new(6), |
| 2971 | rn: FpReg::new(7), |
| 2972 | rm: FpReg::new(8), |
| 2973 | }, |
| 2974 | ); |
| 2975 | } |
| 2976 | #[test] |
| 2977 | fn sys_frintn_2d() { |
| 2978 | verify( |
| 2979 | "frintn.2d v0, v0", |
| 2980 | Inst::FrintnV2D { |
| 2981 | rd: FpReg::new(0), |
| 2982 | rn: FpReg::new(0), |
| 2983 | }, |
| 2984 | ); |
| 2985 | } |
| 2986 | #[test] |
| 2987 | fn sys_frintm_2d() { |
| 2988 | verify( |
| 2989 | "frintm.2d v1, v2", |
| 2990 | Inst::FrintmV2D { |
| 2991 | rd: FpReg::new(1), |
| 2992 | rn: FpReg::new(2), |
| 2993 | }, |
| 2994 | ); |
| 2995 | } |
| 2996 | #[test] |
| 2997 | fn sys_frintp_2d() { |
| 2998 | verify( |
| 2999 | "frintp.2d v3, v4", |
| 3000 | Inst::FrintpV2D { |
| 3001 | rd: FpReg::new(3), |
| 3002 | rn: FpReg::new(4), |
| 3003 | }, |
| 3004 | ); |
| 3005 | } |
| 3006 | #[test] |
| 3007 | fn sys_frintz_2d() { |
| 3008 | verify( |
| 3009 | "frintz.2d v5, v6", |
| 3010 | Inst::FrintzV2D { |
| 3011 | rd: FpReg::new(5), |
| 3012 | rn: FpReg::new(6), |
| 3013 | }, |
| 3014 | ); |
| 3015 | } |
| 3016 | #[test] |
| 3017 | fn sys_frinta_2d() { |
| 3018 | verify( |
| 3019 | "frinta.2d v7, v8", |
| 3020 | Inst::FrintaV2D { |
| 3021 | rd: FpReg::new(7), |
| 3022 | rn: FpReg::new(8), |
| 3023 | }, |
| 3024 | ); |
| 3025 | } |
| 3026 | #[test] |
| 3027 | fn sys_frinti_2d() { |
| 3028 | verify( |
| 3029 | "frinti.2d v9, v10", |
| 3030 | Inst::FrintiV2D { |
| 3031 | rd: FpReg::new(9), |
| 3032 | rn: FpReg::new(10), |
| 3033 | }, |
| 3034 | ); |
| 3035 | } |
| 3036 | #[test] |
| 3037 | fn sys_scvtf_4s() { |
| 3038 | verify( |
| 3039 | "scvtf.4s v0, v1", |
| 3040 | Inst::ScvtfV4S { |
| 3041 | rd: FpReg::new(0), |
| 3042 | rn: FpReg::new(1), |
| 3043 | }, |
| 3044 | ); |
| 3045 | } |
| 3046 | #[test] |
| 3047 | fn sys_ucvtf_4s() { |
| 3048 | verify( |
| 3049 | "ucvtf.4s v2, v3", |
| 3050 | Inst::UcvtfV4S { |
| 3051 | rd: FpReg::new(2), |
| 3052 | rn: FpReg::new(3), |
| 3053 | }, |
| 3054 | ); |
| 3055 | } |
| 3056 | #[test] |
| 3057 | fn sys_fcvtzs_4s() { |
| 3058 | verify( |
| 3059 | "fcvtzs.4s v4, v5", |
| 3060 | Inst::FcvtzsV4S { |
| 3061 | rd: FpReg::new(4), |
| 3062 | rn: FpReg::new(5), |
| 3063 | }, |
| 3064 | ); |
| 3065 | } |
| 3066 | #[test] |
| 3067 | fn sys_fcvtzu_4s() { |
| 3068 | verify( |
| 3069 | "fcvtzu.4s v6, v7", |
| 3070 | Inst::FcvtzuV4S { |
| 3071 | rd: FpReg::new(6), |
| 3072 | rn: FpReg::new(7), |
| 3073 | }, |
| 3074 | ); |
| 3075 | } |
| 3076 | #[test] |
| 3077 | fn sys_frecpe_4s() { |
| 3078 | verify( |
| 3079 | "frecpe.4s v0, v1", |
| 3080 | Inst::FrecpeV4S { |
| 3081 | rd: FpReg::new(0), |
| 3082 | rn: FpReg::new(1), |
| 3083 | }, |
| 3084 | ); |
| 3085 | } |
| 3086 | #[test] |
| 3087 | fn sys_frecps_4s() { |
| 3088 | verify( |
| 3089 | "frecps.4s v2, v3, v4", |
| 3090 | Inst::FrecpsV4S { |
| 3091 | rd: FpReg::new(2), |
| 3092 | rn: FpReg::new(3), |
| 3093 | rm: FpReg::new(4), |
| 3094 | }, |
| 3095 | ); |
| 3096 | } |
| 3097 | #[test] |
| 3098 | fn sys_frsqrte_4s() { |
| 3099 | verify( |
| 3100 | "frsqrte.4s v5, v6", |
| 3101 | Inst::FrsqrteV4S { |
| 3102 | rd: FpReg::new(5), |
| 3103 | rn: FpReg::new(6), |
| 3104 | }, |
| 3105 | ); |
| 3106 | } |
| 3107 | #[test] |
| 3108 | fn sys_frsqrts_4s() { |
| 3109 | verify( |
| 3110 | "frsqrts.4s v7, v8, v9", |
| 3111 | Inst::FrsqrtsV4S { |
| 3112 | rd: FpReg::new(7), |
| 3113 | rn: FpReg::new(8), |
| 3114 | rm: FpReg::new(9), |
| 3115 | }, |
| 3116 | ); |
| 3117 | } |
| 3118 | #[test] |
| 3119 | fn sys_frintn_4s() { |
| 3120 | verify( |
| 3121 | "frintn.4s v0, v1", |
| 3122 | Inst::FrintnV4S { |
| 3123 | rd: FpReg::new(0), |
| 3124 | rn: FpReg::new(1), |
| 3125 | }, |
| 3126 | ); |
| 3127 | } |
| 3128 | #[test] |
| 3129 | fn sys_frintm_4s() { |
| 3130 | verify( |
| 3131 | "frintm.4s v2, v3", |
| 3132 | Inst::FrintmV4S { |
| 3133 | rd: FpReg::new(2), |
| 3134 | rn: FpReg::new(3), |
| 3135 | }, |
| 3136 | ); |
| 3137 | } |
| 3138 | #[test] |
| 3139 | fn sys_frintp_4s() { |
| 3140 | verify( |
| 3141 | "frintp.4s v4, v5", |
| 3142 | Inst::FrintpV4S { |
| 3143 | rd: FpReg::new(4), |
| 3144 | rn: FpReg::new(5), |
| 3145 | }, |
| 3146 | ); |
| 3147 | } |
| 3148 | #[test] |
| 3149 | fn sys_frintz_4s() { |
| 3150 | verify( |
| 3151 | "frintz.4s v6, v7", |
| 3152 | Inst::FrintzV4S { |
| 3153 | rd: FpReg::new(6), |
| 3154 | rn: FpReg::new(7), |
| 3155 | }, |
| 3156 | ); |
| 3157 | } |
| 3158 | #[test] |
| 3159 | fn sys_frinta_4s() { |
| 3160 | verify( |
| 3161 | "frinta.4s v0, v1", |
| 3162 | Inst::FrintaV4S { |
| 3163 | rd: FpReg::new(0), |
| 3164 | rn: FpReg::new(1), |
| 3165 | }, |
| 3166 | ); |
| 3167 | } |
| 3168 | #[test] |
| 3169 | fn sys_frinti_4s() { |
| 3170 | verify( |
| 3171 | "frinti.4s v2, v3", |
| 3172 | Inst::FrintiV4S { |
| 3173 | rd: FpReg::new(2), |
| 3174 | rn: FpReg::new(3), |
| 3175 | }, |
| 3176 | ); |
| 3177 | } |
| 3178 | #[test] |
| 3179 | fn sys_and_16b() { |
| 3180 | verify( |
| 3181 | "and.16b v6, v7, v8", |
| 3182 | Inst::AndV16B { |
| 3183 | rd: FpReg::new(6), |
| 3184 | rn: FpReg::new(7), |
| 3185 | rm: FpReg::new(8), |
| 3186 | }, |
| 3187 | ); |
| 3188 | } |
| 3189 | #[test] |
| 3190 | fn sys_bif_16b() { |
| 3191 | verify( |
| 3192 | "bif.16b v0, v1, v2", |
| 3193 | Inst::BifV16B { |
| 3194 | rd: FpReg::new(0), |
| 3195 | rn: FpReg::new(1), |
| 3196 | rm: FpReg::new(2), |
| 3197 | }, |
| 3198 | ); |
| 3199 | } |
| 3200 | #[test] |
| 3201 | fn sys_bit_16b() { |
| 3202 | verify( |
| 3203 | "bit.16b v3, v4, v5", |
| 3204 | Inst::BitV16B { |
| 3205 | rd: FpReg::new(3), |
| 3206 | rn: FpReg::new(4), |
| 3207 | rm: FpReg::new(5), |
| 3208 | }, |
| 3209 | ); |
| 3210 | } |
| 3211 | #[test] |
| 3212 | fn sys_bic_16b() { |
| 3213 | verify( |
| 3214 | "bic.16b v5, v6, v7", |
| 3215 | Inst::BicV16B { |
| 3216 | rd: FpReg::new(5), |
| 3217 | rn: FpReg::new(6), |
| 3218 | rm: FpReg::new(7), |
| 3219 | }, |
| 3220 | ); |
| 3221 | } |
| 3222 | #[test] |
| 3223 | fn sys_bsl_16b() { |
| 3224 | verify( |
| 3225 | "bsl.16b v6, v7, v8", |
| 3226 | Inst::BslV16B { |
| 3227 | rd: FpReg::new(6), |
| 3228 | rn: FpReg::new(7), |
| 3229 | rm: FpReg::new(8), |
| 3230 | }, |
| 3231 | ); |
| 3232 | } |
| 3233 | #[test] |
| 3234 | fn sys_cmeq_4s() { |
| 3235 | verify( |
| 3236 | "cmeq.4s v0, v0, v1", |
| 3237 | Inst::CmeqV4S { |
| 3238 | rd: FpReg::new(0), |
| 3239 | rn: FpReg::new(0), |
| 3240 | rm: FpReg::new(1), |
| 3241 | }, |
| 3242 | ); |
| 3243 | } |
| 3244 | #[test] |
| 3245 | fn sys_fcmeq_4s() { |
| 3246 | verify( |
| 3247 | "fcmeq.4s v0, v1, v2", |
| 3248 | Inst::FcmeqV4S { |
| 3249 | rd: FpReg::new(0), |
| 3250 | rn: FpReg::new(1), |
| 3251 | rm: FpReg::new(2), |
| 3252 | }, |
| 3253 | ); |
| 3254 | } |
| 3255 | #[test] |
| 3256 | fn sys_fcmeq_2d() { |
| 3257 | verify( |
| 3258 | "fcmeq.2d v0, v1, v2", |
| 3259 | Inst::FcmeqV2D { |
| 3260 | rd: FpReg::new(0), |
| 3261 | rn: FpReg::new(1), |
| 3262 | rm: FpReg::new(2), |
| 3263 | }, |
| 3264 | ); |
| 3265 | } |
| 3266 | #[test] |
| 3267 | fn sys_cmhs_4s() { |
| 3268 | verify( |
| 3269 | "cmhs.4s v0, v0, v1", |
| 3270 | Inst::CmhsV4S { |
| 3271 | rd: FpReg::new(0), |
| 3272 | rn: FpReg::new(0), |
| 3273 | rm: FpReg::new(1), |
| 3274 | }, |
| 3275 | ); |
| 3276 | } |
| 3277 | #[test] |
| 3278 | fn sys_cmhi_4s() { |
| 3279 | verify( |
| 3280 | "cmhi.4s v2, v3, v4", |
| 3281 | Inst::CmhiV4S { |
| 3282 | rd: FpReg::new(2), |
| 3283 | rn: FpReg::new(3), |
| 3284 | rm: FpReg::new(4), |
| 3285 | }, |
| 3286 | ); |
| 3287 | } |
| 3288 | #[test] |
| 3289 | fn sys_cmge_4s() { |
| 3290 | verify( |
| 3291 | "cmge.4s v5, v6, v7", |
| 3292 | Inst::CmgeV4S { |
| 3293 | rd: FpReg::new(5), |
| 3294 | rn: FpReg::new(6), |
| 3295 | rm: FpReg::new(7), |
| 3296 | }, |
| 3297 | ); |
| 3298 | } |
| 3299 | #[test] |
| 3300 | fn sys_fcmge_4s() { |
| 3301 | verify( |
| 3302 | "fcmge.4s v3, v4, v5", |
| 3303 | Inst::FcmgeV4S { |
| 3304 | rd: FpReg::new(3), |
| 3305 | rn: FpReg::new(4), |
| 3306 | rm: FpReg::new(5), |
| 3307 | }, |
| 3308 | ); |
| 3309 | } |
| 3310 | #[test] |
| 3311 | fn sys_fcmge_2d() { |
| 3312 | verify( |
| 3313 | "fcmge.2d v3, v4, v5", |
| 3314 | Inst::FcmgeV2D { |
| 3315 | rd: FpReg::new(3), |
| 3316 | rn: FpReg::new(4), |
| 3317 | rm: FpReg::new(5), |
| 3318 | }, |
| 3319 | ); |
| 3320 | } |
| 3321 | #[test] |
| 3322 | fn sys_cmgt_4s() { |
| 3323 | verify( |
| 3324 | "cmgt.4s v2, v3, v4", |
| 3325 | Inst::CmgtV4S { |
| 3326 | rd: FpReg::new(2), |
| 3327 | rn: FpReg::new(3), |
| 3328 | rm: FpReg::new(4), |
| 3329 | }, |
| 3330 | ); |
| 3331 | } |
| 3332 | #[test] |
| 3333 | fn sys_fcmgt_4s() { |
| 3334 | verify( |
| 3335 | "fcmgt.4s v6, v7, v8", |
| 3336 | Inst::FcmgtV4S { |
| 3337 | rd: FpReg::new(6), |
| 3338 | rn: FpReg::new(7), |
| 3339 | rm: FpReg::new(8), |
| 3340 | }, |
| 3341 | ); |
| 3342 | } |
| 3343 | #[test] |
| 3344 | fn sys_fcmgt_2d() { |
| 3345 | verify( |
| 3346 | "fcmgt.2d v6, v7, v8", |
| 3347 | Inst::FcmgtV2D { |
| 3348 | rd: FpReg::new(6), |
| 3349 | rn: FpReg::new(7), |
| 3350 | rm: FpReg::new(8), |
| 3351 | }, |
| 3352 | ); |
| 3353 | } |
| 3354 | #[test] |
| 3355 | fn sys_fcmge_2d_zero() { |
| 3356 | verify( |
| 3357 | "fcmge.2d v0, v0, #0.0", |
| 3358 | Inst::FcmgeZeroV2D { |
| 3359 | rd: FpReg::new(0), |
| 3360 | rn: FpReg::new(0), |
| 3361 | }, |
| 3362 | ); |
| 3363 | } |
| 3364 | #[test] |
| 3365 | fn sys_fcmgt_2d_zero() { |
| 3366 | verify( |
| 3367 | "fcmgt.2d v1, v1, #0.0", |
| 3368 | Inst::FcmgtZeroV2D { |
| 3369 | rd: FpReg::new(1), |
| 3370 | rn: FpReg::new(1), |
| 3371 | }, |
| 3372 | ); |
| 3373 | } |
| 3374 | #[test] |
| 3375 | fn sys_fcmle_2d_zero() { |
| 3376 | verify( |
| 3377 | "fcmle.2d v2, v2, #0.0", |
| 3378 | Inst::FcmleZeroV2D { |
| 3379 | rd: FpReg::new(2), |
| 3380 | rn: FpReg::new(2), |
| 3381 | }, |
| 3382 | ); |
| 3383 | } |
| 3384 | #[test] |
| 3385 | fn sys_fcmlt_2d_zero() { |
| 3386 | verify( |
| 3387 | "fcmlt.2d v3, v3, #0.0", |
| 3388 | Inst::FcmltZeroV2D { |
| 3389 | rd: FpReg::new(3), |
| 3390 | rn: FpReg::new(3), |
| 3391 | }, |
| 3392 | ); |
| 3393 | } |
| 3394 | #[test] |
| 3395 | fn sys_orr_16b() { |
| 3396 | verify( |
| 3397 | "orr.16b v9, v10, v11", |
| 3398 | Inst::OrrV16B { |
| 3399 | rd: FpReg::new(9), |
| 3400 | rn: FpReg::new(10), |
| 3401 | rm: FpReg::new(11), |
| 3402 | }, |
| 3403 | ); |
| 3404 | } |
| 3405 | #[test] |
| 3406 | fn sys_eor_16b() { |
| 3407 | verify( |
| 3408 | "eor.16b v12, v13, v14", |
| 3409 | Inst::EorV16B { |
| 3410 | rd: FpReg::new(12), |
| 3411 | rn: FpReg::new(13), |
| 3412 | rm: FpReg::new(14), |
| 3413 | }, |
| 3414 | ); |
| 3415 | } |
| 3416 | #[test] |
| 3417 | fn sys_ext_16b() { |
| 3418 | verify( |
| 3419 | "ext.16b v0, v0, v0, #8", |
| 3420 | Inst::ExtV16B { |
| 3421 | rd: FpReg::new(0), |
| 3422 | rn: FpReg::new(0), |
| 3423 | rm: FpReg::new(0), |
| 3424 | index: 8, |
| 3425 | }, |
| 3426 | ); |
| 3427 | } |
| 3428 | #[test] |
| 3429 | fn sys_rev64_4s() { |
| 3430 | verify( |
| 3431 | "rev64.4s v1, v2", |
| 3432 | Inst::Rev64V4S { |
| 3433 | rd: FpReg::new(1), |
| 3434 | rn: FpReg::new(2), |
| 3435 | }, |
| 3436 | ); |
| 3437 | } |
| 3438 | #[test] |
| 3439 | fn sys_zip1_4s() { |
| 3440 | verify( |
| 3441 | "zip1.4s v0, v0, v1", |
| 3442 | Inst::Zip1V4S { |
| 3443 | rd: FpReg::new(0), |
| 3444 | rn: FpReg::new(0), |
| 3445 | rm: FpReg::new(1), |
| 3446 | }, |
| 3447 | ); |
| 3448 | } |
| 3449 | #[test] |
| 3450 | fn sys_zip1_2d() { |
| 3451 | verify( |
| 3452 | "zip1.2d v0, v1, v2", |
| 3453 | Inst::Zip1V2D { |
| 3454 | rd: FpReg::new(0), |
| 3455 | rn: FpReg::new(1), |
| 3456 | rm: FpReg::new(2), |
| 3457 | }, |
| 3458 | ); |
| 3459 | } |
| 3460 | #[test] |
| 3461 | fn sys_zip2_4s() { |
| 3462 | verify( |
| 3463 | "zip2.4s v2, v3, v4", |
| 3464 | Inst::Zip2V4S { |
| 3465 | rd: FpReg::new(2), |
| 3466 | rn: FpReg::new(3), |
| 3467 | rm: FpReg::new(4), |
| 3468 | }, |
| 3469 | ); |
| 3470 | } |
| 3471 | #[test] |
| 3472 | fn sys_zip2_2d() { |
| 3473 | verify( |
| 3474 | "zip2.2d v3, v4, v5", |
| 3475 | Inst::Zip2V2D { |
| 3476 | rd: FpReg::new(3), |
| 3477 | rn: FpReg::new(4), |
| 3478 | rm: FpReg::new(5), |
| 3479 | }, |
| 3480 | ); |
| 3481 | } |
| 3482 | #[test] |
| 3483 | fn sys_uzp1_4s() { |
| 3484 | verify( |
| 3485 | "uzp1.4s v5, v6, v7", |
| 3486 | Inst::Uzp1V4S { |
| 3487 | rd: FpReg::new(5), |
| 3488 | rn: FpReg::new(6), |
| 3489 | rm: FpReg::new(7), |
| 3490 | }, |
| 3491 | ); |
| 3492 | } |
| 3493 | #[test] |
| 3494 | fn sys_uzp1_2d() { |
| 3495 | verify( |
| 3496 | "uzp1.2d v6, v7, v8", |
| 3497 | Inst::Uzp1V2D { |
| 3498 | rd: FpReg::new(6), |
| 3499 | rn: FpReg::new(7), |
| 3500 | rm: FpReg::new(8), |
| 3501 | }, |
| 3502 | ); |
| 3503 | } |
| 3504 | #[test] |
| 3505 | fn sys_uzp2_4s() { |
| 3506 | verify( |
| 3507 | "uzp2.4s v8, v9, v10", |
| 3508 | Inst::Uzp2V4S { |
| 3509 | rd: FpReg::new(8), |
| 3510 | rn: FpReg::new(9), |
| 3511 | rm: FpReg::new(10), |
| 3512 | }, |
| 3513 | ); |
| 3514 | } |
| 3515 | #[test] |
| 3516 | fn sys_uzp2_2d() { |
| 3517 | verify( |
| 3518 | "uzp2.2d v9, v10, v11", |
| 3519 | Inst::Uzp2V2D { |
| 3520 | rd: FpReg::new(9), |
| 3521 | rn: FpReg::new(10), |
| 3522 | rm: FpReg::new(11), |
| 3523 | }, |
| 3524 | ); |
| 3525 | } |
| 3526 | #[test] |
| 3527 | fn sys_trn1_4s() { |
| 3528 | verify( |
| 3529 | "trn1.4s v11, v12, v13", |
| 3530 | Inst::Trn1V4S { |
| 3531 | rd: FpReg::new(11), |
| 3532 | rn: FpReg::new(12), |
| 3533 | rm: FpReg::new(13), |
| 3534 | }, |
| 3535 | ); |
| 3536 | } |
| 3537 | #[test] |
| 3538 | fn sys_trn1_2d() { |
| 3539 | verify( |
| 3540 | "trn1.2d v12, v13, v14", |
| 3541 | Inst::Trn1V2D { |
| 3542 | rd: FpReg::new(12), |
| 3543 | rn: FpReg::new(13), |
| 3544 | rm: FpReg::new(14), |
| 3545 | }, |
| 3546 | ); |
| 3547 | } |
| 3548 | #[test] |
| 3549 | fn sys_trn2_4s() { |
| 3550 | verify( |
| 3551 | "trn2.4s v3, v4, v5", |
| 3552 | Inst::Trn2V4S { |
| 3553 | rd: FpReg::new(3), |
| 3554 | rn: FpReg::new(4), |
| 3555 | rm: FpReg::new(5), |
| 3556 | }, |
| 3557 | ); |
| 3558 | } |
| 3559 | #[test] |
| 3560 | fn sys_trn2_2d() { |
| 3561 | verify( |
| 3562 | "trn2.2d v15, v16, v17", |
| 3563 | Inst::Trn2V2D { |
| 3564 | rd: FpReg::new(15), |
| 3565 | rn: FpReg::new(16), |
| 3566 | rm: FpReg::new(17), |
| 3567 | }, |
| 3568 | ); |
| 3569 | } |
| 3570 | #[test] |
| 3571 | fn sys_tbl_16b_single() { |
| 3572 | verify( |
| 3573 | "tbl.16b v0, { v1 }, v2", |
| 3574 | Inst::TblV16B { |
| 3575 | rd: FpReg::new(0), |
| 3576 | table: FpReg::new(1), |
| 3577 | table_len: 1, |
| 3578 | index: FpReg::new(2), |
| 3579 | }, |
| 3580 | ); |
| 3581 | } |
| 3582 | #[test] |
| 3583 | fn sys_tbl_16b_pair() { |
| 3584 | verify( |
| 3585 | "tbl.16b v3, { v4, v5 }, v6", |
| 3586 | Inst::TblV16B { |
| 3587 | rd: FpReg::new(3), |
| 3588 | table: FpReg::new(4), |
| 3589 | table_len: 2, |
| 3590 | index: FpReg::new(6), |
| 3591 | }, |
| 3592 | ); |
| 3593 | } |
| 3594 | #[test] |
| 3595 | fn sys_tbl_16b_triple() { |
| 3596 | verify( |
| 3597 | "tbl.16b v7, { v8, v9, v10 }, v11", |
| 3598 | Inst::TblV16B { |
| 3599 | rd: FpReg::new(7), |
| 3600 | table: FpReg::new(8), |
| 3601 | table_len: 3, |
| 3602 | index: FpReg::new(11), |
| 3603 | }, |
| 3604 | ); |
| 3605 | } |
| 3606 | #[test] |
| 3607 | fn sys_tbl_16b_quad() { |
| 3608 | verify( |
| 3609 | "tbl.16b v12, { v13, v14, v15, v16 }, v17", |
| 3610 | Inst::TblV16B { |
| 3611 | rd: FpReg::new(12), |
| 3612 | table: FpReg::new(13), |
| 3613 | table_len: 4, |
| 3614 | index: FpReg::new(17), |
| 3615 | }, |
| 3616 | ); |
| 3617 | } |
| 3618 | #[test] |
| 3619 | fn sys_tbx_16b_single() { |
| 3620 | verify( |
| 3621 | "tbx.16b v18, { v19 }, v20", |
| 3622 | Inst::TbxV16B { |
| 3623 | rd: FpReg::new(18), |
| 3624 | table: FpReg::new(19), |
| 3625 | table_len: 1, |
| 3626 | index: FpReg::new(20), |
| 3627 | }, |
| 3628 | ); |
| 3629 | } |
| 3630 | #[test] |
| 3631 | fn sys_tbx_16b_pair() { |
| 3632 | verify( |
| 3633 | "tbx.16b v21, { v22, v23 }, v24", |
| 3634 | Inst::TbxV16B { |
| 3635 | rd: FpReg::new(21), |
| 3636 | table: FpReg::new(22), |
| 3637 | table_len: 2, |
| 3638 | index: FpReg::new(24), |
| 3639 | }, |
| 3640 | ); |
| 3641 | } |
| 3642 | #[test] |
| 3643 | fn sys_mov_16b() { |
| 3644 | verify( |
| 3645 | "mov.16b v0, v2", |
| 3646 | Inst::MovV16B { |
| 3647 | rd: FpReg::new(0), |
| 3648 | rn: FpReg::new(2), |
| 3649 | }, |
| 3650 | ); |
| 3651 | } |
| 3652 | #[test] |
| 3653 | fn sys_mov_8b() { |
| 3654 | verify( |
| 3655 | "mov.8b v1, v3", |
| 3656 | Inst::MovV8B { |
| 3657 | rd: FpReg::new(1), |
| 3658 | rn: FpReg::new(3), |
| 3659 | }, |
| 3660 | ); |
| 3661 | } |
| 3662 | #[test] |
| 3663 | fn sys_mov_4s() { |
| 3664 | verify( |
| 3665 | "mov.4s v4, v5", |
| 3666 | Inst::MovV4S { |
| 3667 | rd: FpReg::new(4), |
| 3668 | rn: FpReg::new(5), |
| 3669 | }, |
| 3670 | ); |
| 3671 | } |
| 3672 | #[test] |
| 3673 | fn sys_mov_2d() { |
| 3674 | verify( |
| 3675 | "mov.2d v6, v7", |
| 3676 | Inst::MovV2D { |
| 3677 | rd: FpReg::new(6), |
| 3678 | rn: FpReg::new(7), |
| 3679 | }, |
| 3680 | ); |
| 3681 | } |
| 3682 | #[test] |
| 3683 | fn sys_fmov_reg_s() { |
| 3684 | verify("fmov s1, s2", Inst::FmovRegS { rd: S1, rn: S2 }); |
| 3685 | } |
| 3686 | #[test] |
| 3687 | fn sys_fmov_reg_d() { |
| 3688 | verify("fmov d1, d2", Inst::FmovRegD { rd: D1, rn: D2 }); |
| 3689 | } |
| 3690 | #[test] |
| 3691 | fn sys_fmov_to_s() { |
| 3692 | verify("fmov s0, w1", Inst::FmovToS { rd: S0, rn: W1 }); |
| 3693 | } |
| 3694 | #[test] |
| 3695 | fn sys_fmov_from_s() { |
| 3696 | verify("fmov w0, s1", Inst::FmovFromS { rd: W0, rn: S1 }); |
| 3697 | } |
| 3698 | #[test] |
| 3699 | fn sys_mov_from_lane_s() { |
| 3700 | verify( |
| 3701 | "mov s0, v1[2]", |
| 3702 | Inst::MovFromLaneS { |
| 3703 | rd: FpReg::new(0), |
| 3704 | rn: FpReg::new(1), |
| 3705 | index: 2, |
| 3706 | }, |
| 3707 | ); |
| 3708 | } |
| 3709 | #[test] |
| 3710 | fn sys_mov_from_lane_d() { |
| 3711 | verify( |
| 3712 | "mov d3, v4[1]", |
| 3713 | Inst::MovFromLaneD { |
| 3714 | rd: FpReg::new(3), |
| 3715 | rn: FpReg::new(4), |
| 3716 | index: 1, |
| 3717 | }, |
| 3718 | ); |
| 3719 | } |
| 3720 | #[test] |
| 3721 | fn sys_mov_lane_s() { |
| 3722 | verify( |
| 3723 | "mov.s v5[0], v6[0]", |
| 3724 | Inst::MovLaneS { |
| 3725 | rd: FpReg::new(5), |
| 3726 | rd_index: 0, |
| 3727 | rn: FpReg::new(6), |
| 3728 | rn_index: 0, |
| 3729 | }, |
| 3730 | ); |
| 3731 | } |
| 3732 | #[test] |
| 3733 | fn sys_mov_lane_d() { |
| 3734 | verify( |
| 3735 | "mov.d v7[1], v8[1]", |
| 3736 | Inst::MovLaneD { |
| 3737 | rd: FpReg::new(7), |
| 3738 | rd_index: 1, |
| 3739 | rn: FpReg::new(8), |
| 3740 | rn_index: 1, |
| 3741 | }, |
| 3742 | ); |
| 3743 | } |
| 3744 | #[test] |
| 3745 | fn sys_mov_lane_h() { |
| 3746 | verify( |
| 3747 | "mov.h v0[5], v1[0]", |
| 3748 | Inst::MovLaneH { |
| 3749 | rd: FpReg::new(0), |
| 3750 | rd_index: 5, |
| 3751 | rn: FpReg::new(1), |
| 3752 | rn_index: 0, |
| 3753 | }, |
| 3754 | ); |
| 3755 | } |
| 3756 | #[test] |
| 3757 | fn sys_mov_lane_b() { |
| 3758 | verify( |
| 3759 | "mov.b v0[7], v1[0]", |
| 3760 | Inst::MovLaneB { |
| 3761 | rd: FpReg::new(0), |
| 3762 | rd_index: 7, |
| 3763 | rn: FpReg::new(1), |
| 3764 | rn_index: 0, |
| 3765 | }, |
| 3766 | ); |
| 3767 | } |
| 3768 | #[test] |
| 3769 | fn sys_mov_from_lane_gp_s() { |
| 3770 | verify( |
| 3771 | "mov.s w0, v1[2]", |
| 3772 | Inst::MovFromLaneGpS { |
| 3773 | rd: W0, |
| 3774 | rn: FpReg::new(1), |
| 3775 | index: 2, |
| 3776 | }, |
| 3777 | ); |
| 3778 | } |
| 3779 | #[test] |
| 3780 | fn sys_mov_from_lane_gp_d() { |
| 3781 | verify( |
| 3782 | "mov.d x0, v1[1]", |
| 3783 | Inst::MovFromLaneGpD { |
| 3784 | rd: X0, |
| 3785 | rn: FpReg::new(1), |
| 3786 | index: 1, |
| 3787 | }, |
| 3788 | ); |
| 3789 | } |
| 3790 | #[test] |
| 3791 | fn sys_umov_h() { |
| 3792 | verify( |
| 3793 | "umov.h w1, v2[5]", |
| 3794 | Inst::UmovFromLaneH { |
| 3795 | rd: W1, |
| 3796 | rn: FpReg::new(2), |
| 3797 | index: 5, |
| 3798 | }, |
| 3799 | ); |
| 3800 | } |
| 3801 | #[test] |
| 3802 | fn sys_umov_b() { |
| 3803 | verify( |
| 3804 | "umov.b w3, v4[7]", |
| 3805 | Inst::UmovFromLaneB { |
| 3806 | rd: W3, |
| 3807 | rn: FpReg::new(4), |
| 3808 | index: 7, |
| 3809 | }, |
| 3810 | ); |
| 3811 | } |
| 3812 | #[test] |
| 3813 | fn sys_smov_h() { |
| 3814 | verify( |
| 3815 | "smov.h w1, v2[3]", |
| 3816 | Inst::SmovFromLaneH { |
| 3817 | rd: W1, |
| 3818 | rn: FpReg::new(2), |
| 3819 | index: 3, |
| 3820 | }, |
| 3821 | ); |
| 3822 | } |
| 3823 | #[test] |
| 3824 | fn sys_smov_b() { |
| 3825 | verify( |
| 3826 | "smov.b w0, v0[0]", |
| 3827 | Inst::SmovFromLaneB { |
| 3828 | rd: W0, |
| 3829 | rn: FpReg::new(0), |
| 3830 | index: 0, |
| 3831 | }, |
| 3832 | ); |
| 3833 | } |
| 3834 | #[test] |
| 3835 | fn sys_mov_lane_from_gp_s() { |
| 3836 | verify( |
| 3837 | "mov.s v5[1], w6", |
| 3838 | Inst::MovLaneFromGpS { |
| 3839 | rd: FpReg::new(5), |
| 3840 | rd_index: 1, |
| 3841 | rn: W6, |
| 3842 | }, |
| 3843 | ); |
| 3844 | } |
| 3845 | #[test] |
| 3846 | fn sys_mov_lane_from_gp_d() { |
| 3847 | verify( |
| 3848 | "mov.d v0[1], x1", |
| 3849 | Inst::MovLaneFromGpD { |
| 3850 | rd: FpReg::new(0), |
| 3851 | rd_index: 1, |
| 3852 | rn: X1, |
| 3853 | }, |
| 3854 | ); |
| 3855 | } |
| 3856 | #[test] |
| 3857 | fn sys_mov_lane_from_gp_h() { |
| 3858 | verify( |
| 3859 | "mov.h v7[5], w8", |
| 3860 | Inst::MovLaneFromGpH { |
| 3861 | rd: FpReg::new(7), |
| 3862 | rd_index: 5, |
| 3863 | rn: W8, |
| 3864 | }, |
| 3865 | ); |
| 3866 | } |
| 3867 | #[test] |
| 3868 | fn sys_mov_lane_from_gp_b() { |
| 3869 | verify( |
| 3870 | "mov.b v9[7], w10", |
| 3871 | Inst::MovLaneFromGpB { |
| 3872 | rd: FpReg::new(9), |
| 3873 | rd_index: 7, |
| 3874 | rn: W10, |
| 3875 | }, |
| 3876 | ); |
| 3877 | } |
| 3878 | #[test] |
| 3879 | fn sys_dup_16b() { |
| 3880 | verify( |
| 3881 | "dup.16b v0, v1[15]", |
| 3882 | Inst::DupV16B { |
| 3883 | rd: FpReg::new(0), |
| 3884 | rn: FpReg::new(1), |
| 3885 | index: 15, |
| 3886 | }, |
| 3887 | ); |
| 3888 | } |
| 3889 | #[test] |
| 3890 | fn sys_dup_8h() { |
| 3891 | verify( |
| 3892 | "dup.8h v1, v2[5]", |
| 3893 | Inst::DupV8H { |
| 3894 | rd: FpReg::new(1), |
| 3895 | rn: FpReg::new(2), |
| 3896 | index: 5, |
| 3897 | }, |
| 3898 | ); |
| 3899 | } |
| 3900 | #[test] |
| 3901 | fn sys_dup_4s() { |
| 3902 | verify( |
| 3903 | "dup.4s v3, v4[2]", |
| 3904 | Inst::DupV4S { |
| 3905 | rd: FpReg::new(3), |
| 3906 | rn: FpReg::new(4), |
| 3907 | index: 2, |
| 3908 | }, |
| 3909 | ); |
| 3910 | } |
| 3911 | #[test] |
| 3912 | fn sys_dup_2d() { |
| 3913 | verify( |
| 3914 | "dup.2d v5, v6[1]", |
| 3915 | Inst::DupV2D { |
| 3916 | rd: FpReg::new(5), |
| 3917 | rn: FpReg::new(6), |
| 3918 | index: 1, |
| 3919 | }, |
| 3920 | ); |
| 3921 | } |
| 3922 | #[test] |
| 3923 | fn sys_fneg_d() { |
| 3924 | verify("fneg d3, d4", Inst::FnegD { rd: D3, rn: D4 }); |
| 3925 | } |
| 3926 | #[test] |
| 3927 | fn sys_fabs_d() { |
| 3928 | verify("fabs d3, d4", Inst::FabsD { rd: D3, rn: D4 }); |
| 3929 | } |
| 3930 | #[test] |
| 3931 | fn sys_fsqrt_d() { |
| 3932 | verify("fsqrt d3, d4", Inst::FsqrtD { rd: D3, rn: D4 }); |
| 3933 | } |
| 3934 | #[test] |
| 3935 | fn sys_fcmp_d() { |
| 3936 | verify("fcmp d3, d4", Inst::FcmpD { rn: D3, rm: D4 }); |
| 3937 | } |
| 3938 | #[test] |
| 3939 | fn sys_fmov_imm_d() { |
| 3940 | verify("fmov d2, #3.50000000", Inst::FmovImmD { rd: D2, imm8: 12 }); |
| 3941 | } |
| 3942 | #[test] |
| 3943 | fn sys_fcsel_d() { |
| 3944 | verify( |
| 3945 | "fcsel d0, d0, d1, mi", |
| 3946 | Inst::FcselD { |
| 3947 | rd: D0, |
| 3948 | rn: D0, |
| 3949 | rm: D1, |
| 3950 | cond: Cond::MI, |
| 3951 | }, |
| 3952 | ); |
| 3953 | } |
| 3954 | #[test] |
| 3955 | fn sys_fmadd_d() { |
| 3956 | verify( |
| 3957 | "fmadd d0, d1, d2, d3", |
| 3958 | Inst::FmaddD { |
| 3959 | rd: D0, |
| 3960 | rn: D1, |
| 3961 | rm: D2, |
| 3962 | ra: D3, |
| 3963 | }, |
| 3964 | ); |
| 3965 | } |
| 3966 | |
| 3967 | // ---- FP / integer conversion ---- |
| 3968 | |
| 3969 | #[test] |
| 3970 | fn sys_fcvtzs() { |
| 3971 | verify("fcvtzs x5, d6", Inst::FcvtzsD { rd: X5, rn: D6 }); |
| 3972 | } |
| 3973 | #[test] |
| 3974 | fn sys_scvtf() { |
| 3975 | verify("scvtf d5, x6", Inst::ScvtfD { rd: D5, rn: X6 }); |
| 3976 | } |
| 3977 | #[test] |
| 3978 | fn sys_fmov_to() { |
| 3979 | verify("fmov d5, x6", Inst::FmovToD { rd: D5, rn: X6 }); |
| 3980 | } |
| 3981 | #[test] |
| 3982 | fn sys_fmov_from() { |
| 3983 | verify("fmov x5, d6", Inst::FmovFromD { rd: X5, rn: D6 }); |
| 3984 | } |
| 3985 | #[test] |
| 3986 | fn sys_fmov_imm_s() { |
| 3987 | verify("fmov s2, #3.50000000", Inst::FmovImmS { rd: S2, imm8: 12 }); |
| 3988 | } |
| 3989 | #[test] |
| 3990 | fn sys_fcsel_s() { |
| 3991 | verify( |
| 3992 | "fcsel s0, s0, s1, mi", |
| 3993 | Inst::FcselS { |
| 3994 | rd: S0, |
| 3995 | rn: S0, |
| 3996 | rm: S1, |
| 3997 | cond: Cond::MI, |
| 3998 | }, |
| 3999 | ); |
| 4000 | } |
| 4001 | |
| 4002 | // ---- System ---- |
| 4003 | |
| 4004 | #[test] |
| 4005 | fn sys_svc() { |
| 4006 | verify("svc #0x80", Inst::Svc { imm16: 0x80 }); |
| 4007 | } |
| 4008 | #[test] |
| 4009 | fn sys_nop() { |
| 4010 | verify("nop", Inst::Nop); |
| 4011 | } |
| 4012 | #[test] |
| 4013 | fn sys_yield() { |
| 4014 | verify("yield", Inst::Yield); |
| 4015 | } |
| 4016 | #[test] |
| 4017 | fn sys_wfe() { |
| 4018 | verify("wfe", Inst::Wfe); |
| 4019 | } |
| 4020 | #[test] |
| 4021 | fn sys_wfi() { |
| 4022 | verify("wfi", Inst::Wfi); |
| 4023 | } |
| 4024 | #[test] |
| 4025 | fn sys_sev() { |
| 4026 | verify("sev", Inst::Sev); |
| 4027 | } |
| 4028 | #[test] |
| 4029 | fn sys_sevl() { |
| 4030 | verify("sevl", Inst::Sevl); |
| 4031 | } |
| 4032 | #[test] |
| 4033 | fn sys_isb() { |
| 4034 | verify( |
| 4035 | "isb", |
| 4036 | Inst::Isb { |
| 4037 | option: BarrierOpt::Sy, |
| 4038 | }, |
| 4039 | ); |
| 4040 | } |
| 4041 | #[test] |
| 4042 | fn sys_dmb_ish() { |
| 4043 | verify( |
| 4044 | "dmb ish", |
| 4045 | Inst::Dmb { |
| 4046 | option: BarrierOpt::Ish, |
| 4047 | }, |
| 4048 | ); |
| 4049 | } |
| 4050 | #[test] |
| 4051 | fn sys_dsb_ishst() { |
| 4052 | verify( |
| 4053 | "dsb ishst", |
| 4054 | Inst::Dsb { |
| 4055 | option: BarrierOpt::Ishst, |
| 4056 | }, |
| 4057 | ); |
| 4058 | } |
| 4059 | #[test] |
| 4060 | fn sys_brk() { |
| 4061 | verify("brk #42", Inst::Brk { imm16: 42 }); |
| 4062 | } |
| 4063 |